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AN2692 Datasheet(PDF) 11 Page - STMicroelectronics |
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AN2692 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 29 page AN2692 Introduction to ST10F269Zx 0.35 µm embedded Flash memory 11/29 1.2.6 Operating modes Unlike the standalone Flash memory, the ST10F269Zx embedded Flash memory has three different operating modes: ● User mode ● Bootstrap mode ● Test mode These modes are selected upon reset by pulling down some specific lines of Port0. Since these modes do not exist in the standalone Flash memory, it is recommended to verify that the embedded Flash memory is in the right mode before erasing or programming it. The EMUCON register shows which operating mode is active. EMUCON(FE0Ah/ 05h) Note: Only 1 of these bits can be active at a time. The three bits are read-only. Before performing any operation on the Flash memory, the user must verify that the Flash memory is really in the desired operating mode: ● To program the Flash memory in the Bootstrap mode, check that the TMOD2 bit is set ● To program the Flash memory in the User mode, check that all TMODx bits are cleared. CP bit Code Protection bit ‘0’: Flash code protection is enabled. Read accesses to the Flash memory or execution not performed in the Flash memory itself are not allowed, the returned value will be 009Bh, whatever the contents of the Flash memory. 1’: Flash code protection is disabled: read accesses to the Flash memory from external or internal RAM are allowed Bit is ‘1’ by default, and can be programmed permanently to ‘0’ using the Set Code Protection command but then cannot be set to ‘1’ again. It is therefore possible to temporally disable the code protection using the Code Temporary Unprotection command. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ----- --- TMOD1 TMOD2 TMOD3 x x x x x RRR TMOD1 bit (EMUCON.7 ) TESTMODE1 Control bit ’0’: TESTMODE1 is not active ’1’: TESTMODE1 is active This bit is set if P0L.2 = 0 during hardware reset. TMOD2 bit (EMUCON.6 ) TESTMODE2 Control bit ’0’: Bootstrap Loader is not active ’1’: Bootstrap Loader is active This bit is set if P0L.[5..3] = 101 during hardware reset. TMOD3 bit (EMUCON.5 ) TESTMODE3 Control bit ’0’: TESTMODE3 is not active ’1’: TESTMODE3 is active This bit is set if P0L.2[5..3] = 100 or 011 during hardware reset. |
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