 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LTC1450 Datasheet(PDF) 7 Page - Linear Technology |
|
||||||||||||||||||||||||||||||
LTC1450 Datasheet(HTML) 7 Page - Linear Technology |
|
|
7 / 16 page  7 LTC1450/LTC1450L PIN FUNCTIONS An input code of (000H) will connect the positive input of the output buffer to this end. Can be used to offset the zero scale above ground. REFHI (Pin 18): Upper input terminal of the DAC’s internal resistor string. Typically connected to REFOUT. An input code of (FFFH) will connect the positive input of the output buffer to 1LSB from this end. REFOUT (Pin 19): Output of the internal 2.048V/1.22V reference. Typically connected to REFHI to drive internal DAC resistor string. VCC (Pin 20): Positive Power Supply Input. 4.5V ≤ VCC ≤ 5.5V (LTC1450) and 2.7V ≤ VCC ≤ 5.5V (LTC1450L). Requires a bypass capacitor to ground. VOUT (Pin 21): Buffered DAC Output. X1/X2 (Pin 22): Gain Setting Resistor Pin. Connect to GND for G = 2 or to VOUT for G = 1. Should always be tied to a low impedance source, such as ground or VOUT, to ensure stability of the output buffer when driving capacitive loads. CLR (Pin 23): Clear Input (Asynchronous Active Low). A low on this pin asynchronously resets all internal latches to 0s. LDAC (Pin 24): Load DAC (Asynchronous Active Low). Used to asynchronously transfer the contents of the input latches to the DAC latches which updates the output voltage. The rising edge latches the data into the DAC latches. If held low the DAC latches are transparent and data from the input latches will immediately update VOUT. WR (Pin 1): Write Input (Active Low). Used with CSMSB and/or CSLSB to load data into the input latches. While WR and CSMSB and/or CSLSB are held low the enabled input latches are transparent. The rising edge of WR will latch data into all input latches. CSLSB (Pin 2): Chip Select Least Significant Byte (Active Low). Used with WR to load data into the eight LSB input latches. While WR and CSLSB are held low the eight LSB input latches are transparent. The rising edge will latch data into the eight LSB input latches. Can be connected to CSMSB for simultaneous loading of both sets of input latches on a 12-bit bus. CSMSB (Pin 3): Chip Select Most Significant Byte (Active Low). Used with WR to load data into the four MSB input latches. While WR and CSMSB are held low the four MSB input latches are transparent. The rising edge will latch data into the four MSB input latches. Can be connected to CSLSB for simultaneous loading of both sets of input latches on a 12-bit bus. D0 to D7 (Pins 4 to 11): Input data for the Least Significant Byte. Loaded into LSB input latch when WR = 0 and CSLSB = 0. D8, D9, D10, D11 (Pins 12, 13, 14, 15): Input data for the Most Significant Byte. Loaded into MSB input latch when WR = 0 and CSMSB = 0. Can be connected to D0 to D3 for multiplexed operation on an 8-bit bus. GND (Pin 16): Ground. REFLO (Pin 17): Lower input terminal of the DAC’s inter- nal resistor string. Typically connected to Analog Ground. |
Similar Part No. - LTC1450 |
|
Similar Description - LTC1450 |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
