3

LTC1569-7

Output DC Offset

±2

±5mV

(Note 2)

±6

±12

mV

±15

mV

Output DC Offset Drift

– 25

µV/°C

– 25

µV/°C

±25

µV/°C

Clock Pin Logic Thresholds

Min Logical “1”

2.6

V

when Clocked Externally

Max Logical “0”

0.5

V

Min Logical “1”

4.0

V

Max Logical “0”

0.5

V

Min Logical “1”

4.0

V

Max Logical “0”

0.5

V

Power Supply Current

6

8

mA

(Note 3)

Pin 5 Open,

q

9mA

7

9

mA

q

10

mA

9

13

mA

q

14

mA

9.5

mA

Pin 5 Shorted to Pin 4,

q

14

mA

20

mA

Pin 5 Shorted to Pin 4,

q

30

mA

27

mA

q

37

mA

Power Supply Voltage where

Pin 5 Shorted to Pin 4, Note 3

q

3.7

4.2

4.6

V

Low Power Mode is Enabled

Clock Feedthrough

0.4

Wideband Noise

125

THD

74

dB

Clock-to-Cutoff

32

Frequency Ratio

Max Clock Frequency

5

MHz

(Note 4)

9.6

MHz

13

MHz

Min Clock Frequency

3V to

kHz

(Note 5)

Input Frequency Range

Aliased Components <–65dB

Hz

ELECTRICAL C

C

HARA TERISTICS

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Note 1: Absolute maximum ratings are those values beyond which the life

of a device may be impaired.

Note 2: DC offset is measured with respect to Pin 3.

Note 3: There are several operating modes which reduce the supply

clock source and the divide-by-4 or divide-by-16 mode is enabled, the

supply current is typically reduced by 60%,relative to divide-by-1 mode,

Note 4: The maximum clock frequency is arbitrarily defined as the

frequency at which the filter AC response exhibits >1dB of gain peaking.

Note 5: The minimum clock frequency is arbitrarily defined as the frequecy

at which the filter DC offset changes by more than 5mV.

Note 6: Thermal resistance varies depending upon the amount of PC board

metal attached to the device.

covered with 2oz copper on both sides.