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AN3202 Datasheet(PDF) 4 Page - STMicroelectronics |
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AN3202 Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 11 page General purpose timers (GPTs) in SPEAr600 AN3202 4/11 Doc ID 17399 Rev 1 The SPEAr600 GPTs always generate precise alarm interrupts, for example in the case of a system tick for a RTOS. Nevertheless, as you can see in Section 2: Reading a free-running timer counter, GPTs can return unpredictable read values when they are running and the input clock is asynchronous (or not in phase). Table 2. GPTx clock source selector Register Address Value GPT1 PRPH_CLK_CFG [08] 0xFCA8_0028 (bit8) 0: PLL3 48 MHz 1: PLL1 (PRSC1_CLK_CFG) GPT2 PRPH_CLK_CFG[09] 0xFCA8_0028 (bit9) 0: PLL3 48 MHz 1: PLL1 (PRSC1_CLK_CFG) GPT3 PRPH_CLK_CFG[10] 0xFCA8_0028 (bit10) 0: PLL3 48 MHz 1: PLL1 (PRSC1_CLK_CFG) GPT4 PRPH_CLK_CFG[11] 0xFCA8_0028 (bit11) 0: PLL3 48 MHz 1: PLL1 (PRSC2_CLK_CFG) GPT5 PRPH_CLK_CFG[12] 0xFCA8_0028 (bit12) 0: PLL3 48 MHz 1: PLL1 (PRSC3_CLK_CFG) |
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