M2V64S20BTP datasheet(2/52 Pages) MITSUBISHI

Part #	M2V64S20BTP

Description	64M bit Synchronous DRAM

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Manufacturer	MITSUBISHI [Mitsubishi Electric Semiconductor]

Direct Link	http://www.mitsubishichips.com

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2 / 52 page

Apr. '99

MITSUBISHI LSIs

MITSUBISHI ELECTRIC

SDRAM (Rev.1.2)

M2V64S20BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 4194304-WORD x 4-BIT)

M2V64S30BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 2097152-WORD x 8-BIT)

M2V64S40BTP-7,-7L,-8,-8L,-8A,-10,-10L (4-BANK x 1048576-WORD x 16-BIT)

64M bit Synchronous DRAM

2

CLK

: Master Clock

CKE

: Clock Enable

/CS

: Chip Select

/RAS

: Row Address Strobe

/CAS

: Column Address Strobe

/WE

: Write Enable

DQ0-3(x4), DQ0-7(x8), DQ0-15(x16)

: Data I/O

DQM (x4, x8) ,DQML/U (x16)

: Output Disable/ Write Mask

A0-11

: Address Input

BA0,1

: Bank Address

Vdd

: Power Supply

VddQ

: Power Supply for Output

Vss

: Ground

VssQ

: Ground for Output

PIN CONFIGURATION (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

Vdd

DQ0

VddQ

DQ2

VssQ

DQ4

VddQ

DQ6

VssQ

Vdd

DQML

/WE

/CAS

/RAS

/CS

BA0(A13)

BA1(A12)

A10

Vss

DQ15

VssQ

DQ13

VddQ

DQ11

VssQ

DQ9

VddQ

Vss

NC

DQMU

CLK

CKE

NC

A11

A8

A7

23

32

24

31

25

30

26

29

27

28

A2

A3

Vdd

A0

A1

A6

A5

A4

Vss

A9

DQ1

DQ3

DQ5

DQ7

DQ8

DQ10

DQ12

DQ14

VddQ

DQ0

VssQ

VddQ

DQ1

VssQ

/CAS

/RAS

BA0(A13)

BA1(A12)

Vdd

NC

Vdd

NC

/WE

/CS

A10

A2

A3

Vdd

A0

A1

NC

Vss

VssQ

NC

DQ3

VddQ

NC

VssQ

NC

DQ2

VddQ

NC

Vss

NC

DQM

CLK

CKE

NC

A11

A8

A7

A6

A5

A4

Vss

A9

NC

Vss

DQ7

VssQ

NC

DQ6

VddQ

NC

DQ5

VssQ

NC

DQ4

VddQ

NC

Vss

NC

DQM

CLK

CKE

NC

A11

A8

A7

A6

A5

A4

Vss

A9

Vdd

DQ0

VddQ

NC

DQ1

VssQ

NC

DQ2

VddQ

NC

DQ3

VssQ

NC

Vdd

NC

/WE

/CAS

/RAS

/CS

BA0(A13)

BA1(A12)

A10

A2

A3

Vdd

A0

A1

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