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PD16721 Datasheet(PDF) 3 Page - Renesas Technology Corp |
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PD16721 Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 30 page The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. © 2000 MOS INTEGRATED CIRCUIT µµµµPD16721 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) DATA SHEET Document No. S14791EJ1V0DS00 (1st edition) Date Published February 2002 NS CP (K) Printed in Japan The mark ! ! ! ! shows major revised points. DESCRIPTION The µPD16721 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. The maximum clock frequency is 70 MHz when driving at 3.0 V. FEATURES • CMOS level input • 384 outputs • Input of 8 bits (gray scale data) by 6 dots • Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter • Logic power supply voltage (VDD1): 2.5 to 3.4 V • Driver power supply voltage (VDD2): 13.0 ± 0.5 V or 15.0 ± 0.5 V (switchable, VSEL) • High-speed data transfer: fCLK. = 70 MHz MAX. (internal data transfer speed when operating at VDD1 = 3.0 V) = 55 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V) • Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Output inversion function (POL21/22) • Output reset control is possible (MODE) • Slew-rate control is possible (SRC) • Output resistance control is possible (ORC) • Single bank arrangement is possible (Loaded with slim TCP) ORDERING INFORMATION Part Number Package µPD16721N-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. 5 5 5 5 5 5 |
Similar Part No. - PD16721_15 |
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Similar Description - PD16721_15 |
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