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LTC3405A-1.375 Datasheet(PDF) 10 Page - Linear Technology |
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LTC3405A-1.375 Datasheet(HTML) 10 Page - Linear Technology |
10 / 12 page 10 LTC3405A-1.375 3405a1375f APPLICATIO S I FOR ATIO where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3405A-1.375 with an input voltage of 2.7V, a load current of 300mA and an ambient temperature of 70°C. From the typical perfor- mance graph of switch resistance, the RDS(ON) of the P- channel switch at 70°C is approximately 0.94Ω and the RDS(ON) of the N-channel synchronous switch is approxi- mately 0.75Ω. The series resistance looking into the SW pin is: RSW = 0.95Ω (0.51) + 0.75Ω (0.49) = 0.85Ω Therefore, power dissipated by the part is: PD = ILOAD2 • RSW = 76.5mW For the SOT-23 package, the θJA is 250°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.0765)(250) = 89.1°C which is well below the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (∆ILOAD • ESR), where ESR is the effective series resistance of COUT. ∆ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady- state value. During this recovery time VOUT can be moni- tored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3405A-1.375. These items are also illustrated graphi- cally in Figures 3 and 4. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. 3. Keep the (–) plates of CIN and COUT as close as possible. Figure 3. LTC3405A-1.375 Layout Diagram RUN LTC3405A-1.375 GND SW 6 L1 BOLD LINES INDICATE HIGH CURRENT PATHS VIN VOUT 3405A1375 F03 4 5 1 3 + – 2 MODE VOUT VIN CIN COUT Design Example As a design example, assume the LTC3405A-1.375 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 0.15A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 1.375V. With this information we can calculate L using equation (1), L fI V V V L OUT OUT IN = () ∆() − ⎛ ⎝ ⎜ ⎞ ⎠ ⎟ 1 1 (3) |
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