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PD160061A Datasheet(PDF) 3 Page - Renesas Technology Corp |
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PD160061A Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 21 page The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. 2003 MOS INTEGRATED CIRCUIT µPD160061A 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 64-GRAY SCALES) DATA SHEET Document No. S16041EJ2V0DS00 (2nd edition) Date Published July 2003 NS CP (K) Printed in Japan DESCRIPTION The µPD160061A is a source driver for TFT-LCDs capable of dealing with displays with 64-gray scales. Data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequency of 65 MHz when driving at 2.7 V, this driver is applicable to XGA-standard TFT-LCD panels and SXGA TFT-LCD panels. FEATURES • CMOS level input (2.3 to 3.6 V) • 384 outputs • Input of 6 bits (gray-scale data) by 6 dots • Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter (R-DAC) • Logic power supply voltage (VDD1): 2.3 to 3.6 V • Driver power supply voltage (VDD2): 7.5 to 9.5 V • High-speed data transfer: fCLK = 65 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.7 V) 40 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.3 V) • Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Input data inversion function (capable of controlling by each input port) (POL21, POL22) • Apply for heavy load, light load • Semi slim-chip shaped ORDERING INFORMATION Part Number Package µPD160061AN-xxx TCP (TAB package) µPD160061ANL-xxx COF (COF package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The mark ★ shows major revised points. |
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