7

LTC1164-6

11646fa

buffer, Figure 3,can be used provided that its input common

mode range is well within the filter’s output swing. Pin 6 is

an intermediate filter output providing an unspecified 6th

order lowpass filter. Pin 6 should not be loaded.

ELLIPTIC/LINEAR PHASE (Pin 10): The DC level at this pin

selects the desired filter response, elliptic or linear phase

and determines the ratio of the clock frequency to the

ratio of 100:1. Pin 10 connected to analog ground pro-

ratio of 160:1 and a transient response overshoot of 1%.

is 50:1 and the filter response is elliptic. Bypassing Pin 10

to analog ground reduces the output DC offsets. If the DC

level at Pin 10 is switched mechanically or electrically at

slew rates greater than 1V/

µswhilethedeviceisoperating,

a 10k resistor should be connected between Pin 10 and the

DC source.

CLK (Pin 11): Any TTL or CMOS clock source with a

square-wave output and 50% duty cycle (

±10%) is an

adequate clock source for the device. The power supply for

the clock source should not be the filter’s power supply.

The analog ground for the filter should be connected to

clock’s ground at a single point only. Table 1 shows the

clock’s low and high level threshold value for a dual or

single supply operation. A pulse generator can be used as

a clock source provided the high level ON time is greater

than 0.5

µs. Sine waves are not recommended for clock

input frequencies less than 100kHz, since excessively

slow clock rise or fall times generate internal clock jitter

(maximum clock rise or fall time

≤ 1µs). The clock signal

should be routed from the right side of the IC package to

avoid coupling into any input or output analog signal path.

A 1k resistor between clock source and Pin 11 will slow

down the rise and fall times of the clock to further reduce

charge coupling, Figures 1 and 2.

1k

1164-6 F03

Figure 3. Buffer for Filter Output

together. In a printed circuit board the connection should

be done under the IC package through a short trace

surrounded by the analog ground plane.

it can typically source or sink 1mA. Driving coaxial cables

or resistive loads less than 20k will degrade the total

harmonicdistortionofthefilter.Whenevaluatingthedevice’s

distortion an output buffer is required. A noninverting

could go above ground, a signal diode must be used to

clamp V. Figures 1 and 2 show typical connections for dual

and single supply operation.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1k

LTC1164-6

DIGITAL SUPPLY

+

GND

CLOCK SOURCE

*

1164-6 F01

* OPTIONAL

0.1

µF

0.1

µF

Table 1. Clock Source High and Low Threshold Levels

POWER SUPPLY

HIGH LEVEL

LOW LEVEL

Dual Supply =

±7.5V

≥ 2.18V

≤ 0.5V

Dual Supply =

±5V

≥ 1.45V

≤ 0.5V

Dual Supply =

±2.5V

≥ 0.73V

≤ – 2.0V

Single Supply = 12V

≥ 7.80V

≤ 6.5V

Single Supply = 5V

≥ 1.45V

≤ 0.5V

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1k

DIGITAL SUPPLY

+

GND

CLOCK SOURCE

1164-6 F02

+

LTC1164-6

0.1

µF

1

µF

10k

10k