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1032E-100LJ Datasheet(PDF) 7 Page - Lattice Semiconductor |
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1032E-100LJ Datasheet(HTML) 7 Page - Lattice Semiconductor |
7 / 16 page 7 Specifications ispLSI and pLSI 1032E GRP Delay, 32 GLB Loads tiobp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Table 2-0036A/1032E Inputs UNITS -100 MIN. MIN. MAX. MAX. DESCRIPTION # 2 PARAM. 22 I/O Register Bypass ns tiolat 23 I/O Latch Delay ns tgrp32 33 ns GLB t1ptxor 36 1 Prod.Term/XOR Path Delay ns t20ptxor 37 20 Prod. Term/XOR Path Delay ns txoradj 38 XOR Adjacent Path Delay ns tgbp 39 GLB Register Bypass Delay ns tgsu 40 GLB Register Setup Time before Clock ns tgh 41 GLB Register Hold Time after Clock ns tgco 42 GLB Register Clock to Output Delay ns 3 tgro 43 GLB Register Reset to Output Delay ns tptre 44 GLB Prod.Term Reset to Register Delay ns tptoe 45 GLB Prod. Term Output Enable to I/O Cell Delay ns tptck 46 GLB Prod. Term Clock Delay ns ORP GRP t4ptbpc 34 4 Prod.Term Bypass Path Delay (Combinatorial) ns t4ptbpr 35 4 Prod. Term Bypass Path Delay (Registered) ns torp 47 ORP Delay ns torpbp 48 ORP Bypass Delay ns tiosu 24 I/O Register Setup Time before Clock ns tioh 25 I/O Register Hold Time after Clock ns tioco 26 I/O Register Clock to Out Delay ns tior 27 I/O Register Reset to Out Delay ns tdin 28 Dedicated Input Delay ns tgrp16 32 GRP Delay, 16 GLB Loads ns tgrp8 31 GRP Delay, 8 GLB Loads ns tgrp4 30 GRP Delay, 4 GLB Loads ns tgrp1 29 GRP Delay, 1 GLB Load ns 0.0 -125 – – – – – – – – – – – – – 0.1 4.5 2.9 – – 3.0 0.0 – – – – – – – 0.3 1.9 3.8 3.6 5.0 5.0 0.4 2.3 4.9 3.9 5.4 3.9 4.0 – – 4.0 1.0 0.0 – – 4.6 4.6 2.3 2.8 2.3 2.0 1.8 – – – – – – – – – – – – – 0.5 5.8 3.5 – – 3.5 0.0 – – – – – – – 0.3 2.3 4.2 4.6 5.8 6.3 1.0 2.5 6.2 4.5 7.2 5.3 5.3 – – 4.7 1.0 – – 5.0 5.0 2.7 3.0 2.4 2.4 1.9 Internal Timing Parameters1 |
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