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1048C Datasheet(PDF) 5 Page - Lattice Semiconductor |
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1048C Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 12 page Specifications ispLSI 1048C/883 5 External Timing Parameters Over Recommended Operating Conditions tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback Clock Frequency, Max Toggle GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Global OE Output Enable Global OE Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 A A A – – – A – – – – A – B C B C – – – – DESCRIPTION1 PARAMETER # 2 -50 MAX. 22.0 26.0 – – – – 14.0 – – 16.0 – 20.5 – 27.5 27.5 20.5 20.5 – – – – ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN. UNITS Table 2- 0030-48C/50 mil – – 50.3 34.5 58.8 13.0 – 0 15.0 – 0 – 13.5 – – – – 8.5 8.5 3.0 9.0 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. Reference Switching Test Conditions section. ( ) 1 twh + tw1 ( ) 1 tsu2 + tco1 TEST 4 COND. |
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