7

Specifications ispLSI and pLSI 1032E

GRP Delay, 32 GLB Loads

1. Internal Timing Parameters are not tested and are for reference only.

2. Refer to Timing Model in this data sheet for further details.

3. The XOR adjacent path can only be used by hard macros.

Table 2-0036A/1032E

Inputs

UNITS

-100

MIN.

MIN.

MAX.

MAX.

DESCRIPTION

#

2

PARAM.

22 I/O Register Bypass

ns

23 I/O Latch Delay

ns

33

ns

GLB

36 1 Prod.Term/XOR Path Delay

ns

ns

38 XOR Adjacent Path Delay

ns

39 GLB Register Bypass Delay

ns

40 GLB Register Setup Time before Clock

ns

41 GLB Register Hold Time after Clock

ns

42 GLB Register Clock to Output Delay

ns

3

43 GLB Register Reset to Output Delay

ns

44 GLB Prod.Term Reset to Register Delay

ns

45 GLB Prod. Term Output Enable to I/O Cell Delay

ns

46 GLB Prod. Term Clock Delay

ns

ORP

GRP

ns

35 4 Prod. Term Bypass Path Delay (Registered)

ns

47 ORP Delay

ns

48 ORP Bypass Delay

ns

24 I/O Register Setup Time before Clock

ns

25 I/O Register Hold Time after Clock

ns

26 I/O Register Clock to Out Delay

ns

27 I/O Register Reset to Out Delay

ns

28 Dedicated Input Delay

ns

32 GRP Delay, 16 GLB Loads

ns

31 GRP Delay, 8 GLB Loads

ns

30 GRP Delay, 4 GLB Loads

ns

29 GRP Delay, 1 GLB Load

ns

0.0

-125

–

–

–

–

–

–

–

–

–

–

–

–

–

0.1

4.5

2.9

–

–

3.0

0.0

–

–

–

–

–

–

–

0.3

1.9

3.8

3.6

5.0

5.0

0.4

2.3

4.9

3.9

5.4

3.9

4.0

–

–

4.0

1.0

0.0

–

–

4.6

4.6

2.3

2.8

2.3

2.0

1.8

–

–

–

–

–

–

–

–

–

–

–

–

–

0.5

5.8

3.5

–

–

3.5

0.0

–

–

–

–

–

–

–

0.3

2.3

4.2

4.6

5.8

6.3

1.0

2.5

6.2

4.5

7.2

5.3

5.3

–

–

4.7

1.0

–

–

5.0

5.0

2.7

3.0

2.4

2.4

1.9