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240VA Datasheet(PDF) 11 Page - Lattice Semiconductor

Part # 240VA
Description  In-System Programmable 3.3V Generic Digital CrosspointTM
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

240VA Datasheet(HTML) 11 Page - Lattice Semiconductor

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11
Specifications ispGDX240VA
7.0
7.0
7.0
11.0
9.0
13.0
8.5
8.5
8.5
8.5
18.0
7.0
0.5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Data Prop. Delay from Any I/O pin to Any I/O Pin (4:1 MUX)
Data Prop. Delay from MUXsel Inputs to Any Output (4:1 MUX)
Clock Frequency, Max. Toggle
Clock Frequency with External Feedback
Input Latch or Register Setup Time Before Y
x
Input Latch or Register Setup Time Before I/O Clock
Output Latch or Register Setup Time Before Y
x
Output Latch or Register Setup Time Before I/O Clock
Global Clock Enable Setup Time Before Y
x
Global Clock Enable Setup Time Before I/O Clock
I/O Clock Enable Setup Time Before Y
x
Input Latch or Reg. Hold Time (Y
x)
Input Latch or Reg. Hold Time (I/O Clock)
Output Latch or Reg. Hold Time (Y
x)
Output Latch or Reg. Hold Time (I/O Clock)
Global Clock Enable Hold Time (Y
x)
Global Clock Enable Hold Time (I/O Clock)
I/O Clock Enable Hold Time (Y
x)
Output Latch or Reg. Clock (from Y
x) to Output Delay
Input Latch or Register Clock (from Y
x) to Output Delay
Output Latch or Register Clock (from I/O pin) to Output Delay
Input Latch or Register Clock (from I/O pin) to Output Delay
Input to Output Enable
Input to Output Disable
Test OE Output Enable
Test OE Output Disable
Clock Pulse Duration, High
Clock Pulse Duration, Low
Register Reset Delay from RESET Low
Reset Pulse Width
Output Delay Adder for Output Timings Using Slow Slew Rate
Output Skew (tgco1 Across Chip)
External Timing Parameters
Over Recommended Operating Conditions
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
80
5.5
4.5
5.5
4.5
3.5
2.5
6.5
0.0
2.5
0.0
2.5
0.0
2.5
0.0
5.0
5.0
14.0
A
A
A
A
A
A
B
C
B
C
D
A
tpd2
tsel2
fmax (Tog.)
fmax (Ext.)
tsu1
tsu2
tsu3
tsu4
tsuce1
tsuce2
tsuce3
th1
th2
th3
th4
thce1
thce2
thce3
tgco12
tgco22
tco12
tco22
ten2
tdis2
ttoeen2
ttoedis2
twh
twl
trst
trw
tsl
tsk
DESCRIPTION
PARAMETER
(
)
1
tsu3+tgco1
UNITS
-7
MIN. MAX.
1. All timings measured with one output switching, fast output slew rate setting, except
tsl.
2. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is
used as I/O voltage reference.
#
4.5
4.5
4.5
8.5
6.0
9.5
6.0
6.0
7.0
7.0
14.0
4.5
0.5
200
111
4.0
3.0
4.0
3.0
2.5
1.5
4.5
0.0
1.5
0.0
1.5
0.0
1.5
0.0
3.5
3.5
10.0
-4
MIN. MAX.
TEST1
COND.


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