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GAL20VP8B-15LP Datasheet(PDF) 11 Page - Lattice Semiconductor |
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GAL20VP8B-15LP Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 17 page Specifications GAL20VP8 11 tpd A Input or I/O to Combinational Output 3 15 3 25 ns tco A Clock to Output Delay 2 10 2 15 ns tcf2 — Clock to Feedback Delay — 4.5 — 10 ns tsu — Setup Time, Input or Feedback before Clock ↑ 8 — 10 — ns th — Hold Time, Input or Feedback after Clock ↑ 0 — 0 — ns A Maximum Clock Frequency with 55.5 — 40 — MHz External Feedback, 1/(tsu + tco) fmax3 A Maximum Clock Frequency with 80 — 50 — MHz Internal Feedback, 1/(tsu + tcf) A Maximum Clock Frequency with 80 — 50 — MHz No Feedback twh — Clock Pulse Duration, High 6 — 10 — ns twl — Clock Pulse Duration, Low 6 — 10 — ns ten B Input or I/O to Output Enabled — 15 — 20 ns B OE to Output Enabled — 12 — 15 ns tdis C Input or I/O to Output Disabled — 15 — 20 ns C OE to Output Disabled — 12 — 15 ns -15 MIN. MAX. PARAMETER UNITS -25 MIN. MAX. TEST COND1. DESCRIPTION 1) Refer to Switching Test Conditions section. 2) Calculated from fmax with internal feedback. Refer to fmax Specification section. 3) Refer to fmax Specification section. SYMBOL PARAMETER MAXIMUM* UNITS TEST CONDITIONS C I Input Capacitance 10 pF V CC = 5.0V, VI = 2.0V C I/O I/O Capacitance 15 pF V CC = 5.0V, VI/O = 2.0V *Characterized but not 100% tested. COM COM AC Switching Characteristics Over Recommended Operating Conditions Capacitance (T A = 25°C, f = 1.0 MHz) |
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