Electronic Components Datasheet Search |
|
GAL26CLV12 Datasheet(PDF) 10 Page - Lattice Semiconductor |
|
GAL26CLV12 Datasheet(HTML) 10 Page - Lattice Semiconductor |
10 / 13 page Specifications GAL26CLV12 10 Electronic Signature An electronic signature (ES) is provided in every GAL26CLV12D device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is al- ways available to the user independent of the state of the security cell. Security Cell A security cell is provided in every GAL26CLV12D device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the de- vice, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Latch-Up Protection GAL26CLV12D devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of suf- ficient magnitude to prevent input undershoots from causing the circuitry to latch. Device Programming GAL devices are programmed using a Lattice Semiconductor- approved Logic Programmer, available from a number of manu- facturers (see the the GAL Development Tools section). Complete programming of the device takes only a few seconds. Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. Typical Input Pull-up Characteristic Input Voltage (V) -80 -70 -60 -50 -40 -30 -20 -10 0 Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an il- legal state (power-up, line voltage glitches, brown-outs, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The GAL26CLV12D device includes circuitry that allows each reg- istered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If nec- essary, approved GAL programmers capable of executing test vec- tors perform output register preload automatically. Input Buffers GAL26CLV12D devices are designed with TTL level compatible in- put buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. The input and I/O pins on the GAL26CLV12D also have built-in ac- tive pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immu- nity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) |
Similar Part No. - GAL26CLV12 |
|
Similar Description - GAL26CLV12 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |