Specifications GAL26CLV12

11

Typ. Vref = Vcc

Typical Output

Typ. Vref = Vcc

Typical Input

Circuitry within the GAL26CLV12D provides a reset signal to all

registers during power-up. All internal registers will have their Q

outputs set low after a specified time (tpr, 1

µs MAX). As a result,

the state on the registered output pins (if they are enabled) will

be either high or low on power-up, depending on the programmed

polarity of the output pins. This feature can greatly simplify state

machine design by providing a known state on power-up. The

timing diagram for power-up is shown below. Because of the asyn-

chronous nature of system power-up, some conditions must be

met to provide a valid power-up reset of the GAL26CLV12D. First,

the Vcc rise must be monotonic. Second, the clock input must

be at static TTL level as shown in the diagram during power up.

The registers will reset within a maximum of tpr time. As in nor-

mal system operation, avoid clocking the device until all input and

feedback path setup times have been met. The clock must also

meet the minimum pulse width requirements.

Vcc

PIN

Vref

Tri-State

Control

Active Pull-up Circuit

Feedback

(To Input Buffer)

PIN

Feedback

Data

Output

Vcc

PIN

Vcc

Vref

Active Pull-up Circuit

ESD

Protection

Circuit

ESD

Protection

Circuit

Vcc

PIN

Vcc (min.)

Internal Register

Reset to Logic "0"

Device Pin

Reset to Logic "1"

Device Pin

Reset to Logic "0"

Vc c

CL K

INTERNAL REGISTER

Q - OUTPUT

ACTIVE LOW

OUTPUT REGISTER

ACTIVE HIGH

OUTPUT REGISTER

Power-Up Reset

Input/Output Equivalent Schematics