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MACH120-12/15

The Macrocell

The MACH120 macrocells can be configured as either registered or combinatorial, with programmable

polarity. The macrocell provides internal feedback whether configured as registered or combinatorial.

The flip-flops can be configured as D-type or T-type, allowing for product-term optimization.

The flip-flops can individually select one of four global clock pins, which are also available as

logic inputs. The registers are clocked on the LOW-to-HIGH transition of the clock signal. The

flip-flops can also be asynchronously initialized with the common asynchronous reset and preset

product terms.

The I/O Cell

The I/O cell in the MACH120 consists of a three-state output buffer. The three-state buffer can

be configured in one of three ways: always enabled, always disabled, or controlled by a product

term. If product term control is chosen, one of two product terms may be used to provide the

control. The two product terms that are available are common to six I/O cells. Within each PAL

block, two product terms are available for selection by the first six three-state outputs; two other

product terms are available for selection by the last six three-state outputs.

These choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or

a three-state output for use in driving a bus.

SpeedLocking for Guaranteed Fixed Timing

The unique MACH 1 architecture is designed for high performance—a metric that is met in both

raw speed, but even more importantly, guaranteed fixed speed. Using the design of the central

switch matrix, the MACH 120 product offers the SpeedLocking feature, which allows a stable

fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for up to

16 product terms per output. Other non-Vantis CPLDs incur serious timing delays as product

terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine

for continuous, high performance required in today's demanding designs