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ISPGDX160-7B272 Datasheet(PDF) 8 Page - Lattice Semiconductor |
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ISPGDX160-7B272 Datasheet(HTML) 8 Page - Lattice Semiconductor |
8 / 25 page 8 Specifications ispGDX Family External Timing Parameters Over Recommended Operating Conditions ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns – – 111 4.0 4.0 0.0 – – – – – – – 3.5 3.5 – 10.0 – – 5.0 6.5 – – – – 5 8.5 6.0 9.5 6.0 6.0 9.0 9.0 – – 14.0 – 5.0 0.5 – – 80.0 5.5 5.5 0.0 – – – – – – – 5.0 5.0 – 14.0 – – 7.0 9.0 – – – – 7.0 11.0 9.0 13.0 8.5 8.5 12.0 12.0 – – 18.0 – 7.0 0.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A A – – – – A A A A B C B C – – – – A A Data Propagation Delay from any I/O pin to any I/O pin Data Propagation Delay from MUXsel Inputs to any Output Clock Frequency with External Feedback Input Latch or Register Setup Time before any Clk Output Latch or Register MUX Data Setup Time before any Clk Latch or Register Hold Time after any Clk Output Latch or Register Clk (from Y x) to Output Delay Input Latch or Register Clk (from Y x) to Output Delay Output Latch or Register Clk (from I/O pin) to Output Delay Input Latch or Register Clock (from I/O pin) to Output Delay Input to Output Enable Input to Output Disable Test OE Output Enable Test OE Output Disable Clock Pulse Duration, High Clock Pulse Duration, Low Register Reset Delay from RESET Low Reset pulse width Output Delay Adder for Output Timings Using Slow Slew Rate Output Skew (tgco1 across chip) tpd tsel fmax(ext) tsu1 tsu2 th tgco1 tgco2 tco1 tco2 ten tdis ttoeen ttoedis twh twl trst trw tsl tsk DESCRIPTION PARAMETER TEST 1 COND. # ( ) 1 tsu2+tgco1 UNITS -5 MIN. MAX. -7 MIN. MAX. 1. All timings measured with one output switching, fast output slew rate setting, except tsl. 2 8 010 4 2030 4050 60 70 I/O Cell Fanout 6 10 4 Maximum ∆ GRP Delay vs. I/O Cell Fanout ispGDX timings are specified with a GRP load (fanout) of four I/O cells. The figure at right shows the Maximum ∆ GRP Delay with increased GRP loads. These deltas apply to any signal path traversing the GRP (MUXA-D, OE, CLK, MUXsel0-1). Global Clock signals, which do not use the GRP, have no fanout delay adder. |
Similar Part No. - ISPGDX160-7B272 |
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Similar Description - ISPGDX160-7B272 |
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