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ISPGDX120A-7T176 Datasheet(PDF) 3 Page - Lattice Semiconductor |
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ISPGDX120A-7T176 Datasheet(HTML) 3 Page - Lattice Semiconductor |
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3 / 25 page  3 Specifications ispGDX Family Architecture The ispGDX architecture is different from traditional PLD architectures, in keeping with its unique application fo- cus. The block diagram is shown below. The programmable interconnect consists of a single Global Routing Pool (GRP). Unlike ispLSI devices, there are no programmable logic arrays on the device. Control signals for OEs, Clocks and MUX Controls must come from designated sets of I/O pins. The polarity of these signals can be independently programmed in each I/O cell. Each I/O cell drives a unique pin. The OE control for each I/O pin is independent and may be driven via the GRP by one of the designated I/O pins (I/O-OE set). The I/O-OE set consists of 25% of the total I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. The in-system programming process uses either a Bound- ary Scan based or Lattice ISP protocol. The programming protocol is selected by the BSCAN/ ispEN pin as de- scribed later. The various I/O pin sets are also shown in the block diagram below. The A, B, C, and D I/O pins are grouped together with one group per side. I/O Architecture Each I/O cell contains a 4:1 dynamic MUX controlled by two select lines called MUX0 and MUX1 as shown in Figure 1. The four data inputs to the MUX (called MUXA, MUXB, MUXC and MUXD) come from I/O signals found in the GRP. Each MUX data input can access one quarter of the total I/Os. For example, in a 160 I/O ispGDX, each data input can connect to one of 40 I/O pins. MUX0 and MUX1 can be driven by designated I/O pins called MUXsel1 and MUXsel2. Each MUXsel input covers 25% of the total I/O pins (e.g. 40 out of 160). MUX0 and MUX1 can be driven from either MUXsel1 or MUXsel2. The I/O cell also includes a programmable flow-through latch or register that can be placed in the input or output path and bypassed for combinatorial outputs. As shown in Figure 1, when both register/latch control MUXes select the “A” path, the register/latch gets its inputs from the 4:1 MUX and drives the I/O output. When selecting the “B” path, the register/latch is directly driven by the I/O input while its output feeds the GRP. The programmable polarity Clock to the latch or register can be connected to any I/O in the I/O-Clock set (one-quarter of total I/Os) or to one of the dedicated clock input pins (Yx). Use of the dedicated clock inputs gives minimum clock-to-output delays and minimizes delay variation with fanout. Com- binatorial output mode may be implemented by a dedicated architecture bit and bypass MUX. I/O cell output polarity can be programmed as active high or active low. Figure 1. ispGDX I/O Cell and GRP Detail (160 I/O Device) I/O 0 I/O 1 I/O 78 I/O 79 80 I/O Cells Boundary Scan Cell Bypass Option I/O Cell N Register or Latch I/O Pin Prog. Pull-up Programmable Slew Rate D A B CLK Reset Q 4-to-1 MUX 160 Input GRP Inputs Vertical Outputs Horizontal I/O 80 I/O 81 I/O 158 MUXA MUXB MUXC MUXD MUX1 MUX0 Global Reset I/O 159 • • • • • • • • • 80 I/O Cells • • • • • • E2CMOS Programmable Interconnect Logic "1" 160 I/O Inputs C R Y0-Y3 Global Clocks I/O MUX Operation MUX1 MUX0 DATA INPUT SELECTED 0 0 MUXA 0 1 MUXB 1 1 MUXC 1 0 MUXD |
Similar Part No. - ISPGDX120A-7T176 |
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Similar Description - ISPGDX120A-7T176 |
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