GAL20V8

Generic Array Logic™

1

228

I

I

I

I

I

I

NC

NC

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

4

5

7

9

11

12

14

16

18

19

21

23

25

26

PLCC

1

12

13

24

I/CLK

I

I

I

I

I

I

I

I

I

I

GND

Vcc

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

I/OE

6

18

GAL20V8

Top View

GAL

20V8

DIP

CLK

I

I

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I/O/Q

I

I

I

I

I

I

I

I

I

I

I/OE

I/CLK

OE

8

8

8

8

8

8

8

8

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

OLMC

IMUX

IMUX

OLMC

Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

August 2000

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

20v8_04

Features

— 5 ns Maximum Propagation Delay

— Fmax = 166 MHz

— 4 ns Maximum from Clock Input to Data Output

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 75mA Typ Icc on Low Power Device

— 45mA Typ Icc on Quarter Power Device

• ACTIVE PULL-UPS ON ALL PINS

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

Fuse Map/Parametric Compatibility

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

The GAL20V8C, at 5ns maximum propagation delay time, com-

bines a high performance CMOS process with Electrically Eras-

performance available in the PLD market. High speed erase times

(<100ms) allow the devices to be reprogrammed quickly and ef-

ficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configura-

tions possible with the GAL20V8 are the PAL architectures listed

in the table of the macrocell description section. GAL20V8 devices

are capable of emulating any of these PAL architectures with full

function/fuse map/parametric compatibility.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

Functional Block Diagram

Pin Configuration