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UPD750066CU Datasheet(PDF) 10 Page - NEC |
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UPD750066CU Datasheet(HTML) 10 Page - NEC |
10 / 82 page 10 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet U10165EJ2V0DS00 3.2 Non-port Pins (1/2) Pin Name Input/Output Alternate Function After Reset I/O Circuit Function TypeNote TI0 Input P13 Inputs external event pulses to the timer/event Input <B>-C TI1 P12/INT2 counter. PTO0 Output P20 Timer/event counter output Input E-B PTO1 P21 PCL P22 Clock output BUZ P23 Optional frequency output (for buzzer output or system clock trimming) SCK Input/Output P01 Serial clock input/output Input <F>-A SO Output P02 Serial data output <F>-B SB0 Input/Output Serial data bus input/output SI Input P03 Serial data input <M>-C SB1 Input/Output Serial data bus input/output INT4 Input P00 Edge detection vectored interrupt input (both <B> rising edge and falling edge detection) INT0 Input P10 Input <B>-C INT1 P11 Asynchronous INT2 Input P12/TI1 Rising edge detection Asynchronous Input <B>-C testable input KR0 to KR3 Input P60/AN4 to Falling edge detection testable input Input <Y>-D P63/AN7 AN0 to AN3 Input P110 to P113 Analog signal input Input Y-A AN4 to AN7 P60/KR0 to <Y>-D P63/KR3 AVREF – – A/D converter reference voltage – Z-N AVSS – – A/D converter reference GND potential – Z-N Note Circuit types enclosed in brackets indicate the Schmitt trigger input. Edge detection vectored Noise elimination interrupt input (detection circuit/asynchronous edge can be selected). selection INT0/P10 can select noise elimination circuit. |
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