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UPD75036 Datasheet(PDF) 9 Page - NEC |
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UPD75036 Datasheet(HTML) 9 Page - NEC |
9 / 58 page 9 µPD75036 3.2 NON-PORT PINS (1/2) Pin TI0 PTO0 PCL BUZ SCK SO/SB0 SI/SB1 INT4 INT0 INT1 INT2 KR0 - KR3 KR4-KR7 MAR MAI MAZ MAT PPO AN0 - AN3 AN4 - AN7 AVREF+ AVREF- AVDD AVSS I/O circuit typeNote 1 F-C E-B E-B E-B F-A F-B F-C F-C F-C F-A F-A M M M M E-B Y-A Y Z-A Z-A – – Shared pin P13 P20 P22 P23 P01 P02 P03 P00 P10 P11 P12 P60 - P63 P70 - P73 P100 P101 P102 P103 P21 P110 - P113 – – – – – When reset – Input Input Input Input Input Input – – – Input Input Note 4 Note 4 Note 4 Note 4 Input Input – – – – Input/ output Input I/O I/O I/O I/O I/O I/O Input Input Input I/O I/O I/O I/O I/O I/O I/O Input Input Input – – Function Input for receiving external event pulse signal for timer/event counter Timer/event counter output Clock output Output for arbitrary frequency output (for buzzer output or system clock trimming) Serial clock I/O Serial data output Serial bus I/O Serial data input Serial bus I/O Edge detection vectored interrupt input (either rising edge or falling edge detection) Edge detection vectored interrupt input (detection edge selectable) Edge detection testable input (rising edge detection) Parallel falling edge detection testable input Parallel falling edge detection testable input In MFT integral A/D converter mode In MFT timer mode For A /D converter only Note 2 Note 3 Note 3 Reverse integration signal output Integration signal output Autozero signal output Comparator input Timer pulse output 8-bit analog input Reference voltage input (on AVDD side) Reference voltage input (on AVSS side) Operating power supply Reference GND potential Notes 1. The circle ( ) indicates the Schmitt trigger input. 2. Clock synchronous 3. Asynchronous 4. High level (when pull-up resistors are provided) or high impedance Remark MFT: Multifunction Timer B F F M B B B F F |
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Similar Description - UPD75036 |
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