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MACH131SP-7YC Datasheet(PDF) 11 Page - Lattice Semiconductor |
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MACH131SP-7YC Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 48 page MACH 1 & 2 Families 11 The flip-flops in either macrocell type can be clocked by one of several clock pins (Table 10). Registers are clocked on the rising edge of the clock input. Latches hold their data when the gate input is HIGH. Clock pins are also available as inputs, although care must be taken when a signal acts as both clock and input to the same device. All flip-flops have asynchronous reset and preset. This is controlled by the common product terms that control all flip-flops within a PAL block. For a single PAL block, all flip-flops, whether in an output or a buried macrocell, are initialized together. The initialization functionality of the flip-flops is illustrated in Table 11. I/O Cells The I/O cells (Figure 7) provide a three-state output buffer. The three-state buffer can be left permanently enabled for use only as an output, permanently disabled for use as an input, or it can be controlled by one of two product terms for bi-directional signals and bus connections. The two product terms provided are common to a bank of I/O cells. Table 10. Macrocell Clocks Device Number of Clocks Available Device Number of Clocks Available MACH111 4 MACH211SP 2 MACH111SP 2 MACH221 4 MACH131 4 MACH221SP 4 MACH131SP 4 MACH231 4 MACH211 4 MACH231SP 4 Table 11. Asynchronous Reset/Preset Operation Configuration AR AP CLK/LE Q+ Register 0 0 X See Table 9 01 X 1 10 X 0 11 X 0 Latch 0 0 X See Table 9 0 1 0 Illegal 01 1 1 1 0 0 Illegal 10 1 0 1 1 0 Illegal 11 1 0 |
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