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LT1425 Datasheet(PDF) 9 Page - Linear Technology |
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LT1425 Datasheet(HTML) 9 Page - Linear Technology |
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9 / 20 page  9 LT1425 OPERATION Effects of Variable Enable Period It should now be clear that the flyback amplifier is enabled only during a portion of the cycle time. This can vary from the fixed “minimum enable time” described to a maximum of roughly the OFF switch time minus the enable delay time. Certain parameters of flyback amp behavior will then be directly affected by the variable enable period. These include effective transconductance and VC node slew rate. LOAD COMPENSATION THEORY The LT1425 uses the flyback pulse to obtain information about the isolated output voltage. A potential error source is caused by transformer secondary current flow through the real life nonzero impedances of the output rectifier, transformer secondary and output capacitor. This has been represented previously by the expression (ISEC)(ESR). However, it is generally more useful to convert this expres- sion to an effective output impedance. Because the sec- ondary current only flows during the off portion of the duty cycle, the effective output impedance equals the lumped secondary impedance times the inverse of the OFF duty cycle. That is, ROUT = ESR where, ROUT = Effective supply output impedance ESR = Lumped secondary impedance DC OFF = OFF duty cycle 1 DC OFF ) ) Expressing this in terms of the ON duty cycle, remember- ing DC OFF = 1 – DC, ROUT = ESR DC = ON duty cycle 1 1 – DC ) ) In less critical applications, or if output load current remains relatively constant, this output impedance error may be judged acceptable and the external RFB resistor value adjusted to compensate for nominal expected error. In more demanding applications, output impedance error regulation. See Applications Information section for fur- ther details. Enable Delay When the output switch shuts off, the flyback pulse appears. However, it takes a finite time until the trans- former primary side voltage waveform approximately rep- resents the output voltage. This is partly due to rise time on the VSW node, but more importantly due to transformer leakage inductance. The latter causes a voltage spike on the primary side not directly related to output voltage. (Some time is also required for internal settling of the feedback amplifier circuitry.) In order to maintain immunity to these phenomena, a fixed delay is introduced between the switch turn-off command and the enabling of the feedback amplifier. This is termed “enable delay.” In certain cases where the leakage spike is not sufficiently settled by the end of the enable delay period, regulation error may result. See Applications Information section for further details. Collapse Detect Once the feedback amplifier is enabled, some mechanism is then required to disable it. This is accomplished by a collapse detect comparator, that compares the flyback voltage (RREF referred) to a fixed reference, nominally 80% of VBG. When the flyback waveform drops below this level, the feedback amplifier is disabled. This action accommodates both continuous and discontinuous mode operation. Minimum Enable Time The feedback amplifier, once enabled, stays enabled for a fixed minimum time period termed “minimum enable time.” This prevents lock-up, especially when the output voltage is abnormally low, e.g., during start-up. The mini- mum enable time period ensures that the VC node is able to “pump up” and increase the current mode trip point to the level where the collapse detect system exhibits proper operation. The “minimum enable time” often determines the low load level at which output voltage regulation is lost. See Applications Information section for details. |
Similar Part No. - LT1425_15 |
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Similar Description - LT1425_15 |
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