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UPD750068CU Datasheet(PDF) 7 Page - NEC |
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UPD750068CU Datasheet(HTML) 7 Page - NEC |
7 / 82 page 7 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet U10165EJ2V0DS00 2. BLOCK DIAGRAM Note The ROM capacity varies depending on the product. Basic interval timer/watchdog timer Watch timer 8-bit timer/ event counter#0 8-bit timer/ event counter#1 Cascaded 16-bit timer/ event counter Clocked serial interface Interrupt control A/D converter INTBT INTW INTT0 INTW INTT1 TOUT0 INTCSI BUZ/P23 TI0/P13 PTO0/P20 TI1/P12/INT2 PTO1/P21 SI/SB1/P03 SO/SB0/P02 SCK/P01 INT0/P10 INT1/P11 INT4/P00 INT2/P12/TI1 KR0/P60 to KR3/P63 AN0/P110 to AN3/P113 AN4/P60 to AN7/P63 AVREF AVSS CY SP (8) SBS BANK Program counter Program memoryNote (ROM) Decode and control General reg. Data memory (RAM) 512 × 4 bits Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 11 Bit seq. buffer (16) P00 to P03 4 4 4 4 4 4 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P110 to P113 fx/2N CPU Clock Φ Clock output control Clock divider Sub Main System clock generator Stand by control PCL/P22 XT1 XT2 X1 X2 IC VDD VSS RESET ALU 4 4 4 4 4 |
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