MACH111-12JI datasheet(7/48 Pages) LATTICE

Part #	MACH111-12JI

Description	High-Performance EE CMOS Programmable Logic

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MACH 1 & 2 Families

7

Macrocell

There are two fundamental types of macrocell: the output macrocell and the buried macrocell. The

buried macrocell is only found in MACH 2 devices. The use of buried macrocells effectively

doubles the number of macrocells available without increasing the pin count.

Both macrocell types can generate registered or combinatorial outputs. For the MACH 2 series,

a transparent-low latch conﬁguration is provided. If the register is used, it can be conﬁgured as

a T-type or a D-type ﬂip-ﬂop. Register and latch functionality is deﬁned in Table 9.

Programmable polarity (for output macrocells) and the T-type ﬂip-ﬂop both give the software a

way to minimize the number of product terms needed. These choices can be made automatically

by the software when it ﬁts the design into the device.

Table 7. Logic Allocation for MACH211(SP) and MACH231(SP)

Macrocell

Available Clusters

Macrocell

Available Clusters

Output

Buried

Output

Buried

M0

M1

C0, C1, C2

C0, C1, C2, C3

M8

M9

C7, C8, C9, C10

C8, C9, C10, C11

M2

M3

C1, C2, C3, C4

C2, C3, C4, C5

M10

M11

C9, C10, C11, C12

C10, C11, C12, C13

M4

M5

C3, C4, C5, C6

C4, C5, C6, C7

M12

M13

C11, C12, C13, C14

C12, C13, C14, C15

M6

M7

C5, C6, C7, C8

C6, C7, C8, C9

M14

M15

C13, C14, C15

C14, C15

Table 8. Logic Allocation for MACH221(SP)

Macrocell

Available Clusters

Macrocell

Available Clusters

Output

Buried

Output

Buried

M0

M1

C0, C1, C2

C0, C1, C2, C3

M6

M7

C5, C6, C7, C8

C6, C7, C8, C9

M2

M3

C1, C2, C3, C4

C2, C3, C4, C5

M8

M9

C7, C8, C9, C10

C8, C9, C10, C11

M4

M5

C3, C4, C5, C6

C4, C5, C6, C7

M10

M11

C9, C10, C11

C10, C11

Table 9. Register/Latch Operation

Conﬁguration

D/T

CLK/LE

Q+

D-Register

X

0,1,

↓

Q

0

↑

0

1

↑

1

T-Register

X

0,1,

↓

Q

0

↑

Q

1

↑

Q

Latch

X1

Q

00

0

10

1

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