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MACH221-12JI Datasheet(PDF) 4 Page - Lattice Semiconductor |
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MACH221-12JI Datasheet(HTML) 4 Page - Lattice Semiconductor |
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4 / 48 page  4 MACH 1 & 2 Families FUNCTIONAL DESCRIPTION Each MACH 1 and 2 device consists of multiple, optimized PAL® blocks interconnected by a switch matrix. The switch matrix allows communication between PAL blocks, and routes inputs to the PAL blocks. Together, the PAL blocks and switch matrix allow the logic designer to create large designs in a single device instead of using multiple devices. The switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the switch matrix. This mechanism ensures that PAL blocks in MACH devices communicate with each other with guaranteed fixed timing (SpeedLocking). The switch matrix makes a MACH device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. 14051K-002 Figure 1. Overall Architecture of MACH 1 & 2 Devices Array and Allocator Output Macrocells Buried Macrocells I/O Cells Buried Macrocell Feedback Output Macrocell Feedback I/O Pin Feedback I/O Pins PAL Block I/O Pins PAL Block PAL Block Clock/Input Pins Dedicated Input Note: 1. There are no buried macrocells in MACH 1 devices. All macrocells are output macrocells. PAL Block Device PAL Blocks Macrocells per Block I/Os per Block Product Terms per Block MACH111(SP) 21616 70 MACH131(SP) 41616 70 MACH211(SP) 416 8 68 MACH221(SP) 812 6 52 MACH231(SP) 816 8 68 (note 1) I/O Pins I/O Pins |
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Similar Description - MACH221-12JI |
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