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LT1171M Datasheet(PDF) 8 Page - Linear Technology |
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LT1171M Datasheet(HTML) 8 Page - Linear Technology |
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8 / 20 page  8 LT1170/LT1171/LT1172 function; when pulled low with an external resistor, it programs the LT1170/LT1171/LT1172 to disconnect the main error amplifier output and connects the output of the flyback amplifier to the comparator input. The LT1170/ LT1171/LT1172 will then regulate the value of the flyback pulse with respect to the supply voltage.* This flyback pulse is directly proportional to output voltage in the traditional transformer coupled flyback topology regula- tor. By regulating the amplitude of the flyback pulse, the output voltage can be regulated with no direct connection between input and output. The output is fully floating up to the breakdown voltage of the transformer windings. Mul- tiple floating outputs are easily obtained with additional windings. A special delay network inside the LT1170/ LT1171/LT1172 ignores the leakage inductance spike at the leading edge of the flyback pulse to improve output regulation. The error signal developed at the comparator input is brought out externally. This pin (VC) has four different functions. It is used for frequency compensation, current limit adjustment, soft starting, and total regulator shut- down. During normal regulator operation this pin sits at a voltage between 0.9V (low output current) and 2.0V (high output current). The error amplifiers are current output (gm) types, so this voltage can be externally clamped for adjusting current limit. Likewise, a capacitor coupled external clamp will provide soft start. Switch duty cycle goes to zero if the VC pin is pulled to ground through a diode, placing the LT1170/LT1171/LT1172 in an idle mode. Pulling the VC pin below 0.15V causes total regulator shutdown, with only 50 µA supply current for shutdown circuitry biasing. See AN19 for full application details. Extra Pins on the MiniDIP and Surface Mount Packages The 8- and 16-pin versions of the LT1172 have the emitters of the power transistor brought out separately from the ground pin. This eliminates errors due to ground pin voltage drops and allows the user to reduce switch current limit 2:1 by leaving the second emitter (E2) discon- nected. The first emitter (E1) should always be connected to the ground pin. Note that switch “on” resistance doubles when E2 is left open, so efficiency will suffer somewhat when switch currents exceed 300mA. Also, note that chip dissipation will actually increase with E2 open during normal load operation, even though dissipation in current limit mode will decrease. See “Thermal Considerations” next. Thermal Considerations When Using the MiniDIP and SW Packages The low supply current and high switch efficiency of the LT1172 allow it to be used without a heat sink in most applications when the TO-220 or TO-3 package is se- lected. These packages are rated at 50 °C/W and 35°C/W respectively.The miniDIPs, however,are rated at 100 °C/W in ceramic (J) and 130 °C/W in plastic (N). Care should be taken for miniDIP applications to ensure that the worst case input voltage and load current condi- tions do not cause excessive die temperatures. The follow- ing formulas can be used as a rough guide to calculate LT1172 power dissipation. For more details, the reader is referred to Application Note 19 (AN19), “Efficiency Calcu- lations” section. Average supply current (including driver current) is: IIN ≈ 6mA + ISW(0.004 + DC/40) ISW = switch current DC = switch duty cycle Switch power dissipation is given by: PSW = (ISW)2 • (RSW)(DC) RSW = LT1172 switch “on” resistance (1Ω maximum) Total power dissipation is the sum of supply current times input voltage plus switch power: PD(TOT) = (IIN)(VIN) + PSW In a typical example, using a boost converter to generate 12V at 0.12A from a 5V input, duty cycle is approximately 60%, and switch current is about 0.65A, yielding: IIN = 6mA + 0.65(0.004 + DC/40) = 18mA PSW = (0.65)2 • (1Ω)(0.6) = 0.25W PD(TOT) = (5V)(0.018A) + 0.25 = 0.34W *See note under block diagram. OPERATIO |
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