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LT1171CK Datasheet(PDF) 9 Page - Linear Technology |
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LT1171CK Datasheet(HTML) 9 Page - Linear Technology |
9 / 20 page 9 LT1170/LT1171/LT1172 Temperature rise in a plastic miniDIP would be 130 °C/W times 0.34W, or approximately 44 °C. The maximum am- bient temperature would be limited to 100 °C (commercial temperature limit) minus 44 °C, or 56°C. In most applications, full load current is used to calculate die temperature. However, if overload conditions must also be accounted for, four approaches are possible. First, if loss of regulated output is acceptable under overload conditions, the internal thermal limit of the LT1172 will protect the die in most applications by shutting off switch current. Thermal limit is not a tested parameter, however, and should be considered only for noncritical applications with temporary overloads. A second approach is to use the larger TO-220 (T) or TO-3 (K) package which, even without a heat sink, may limit die temperatures to safe levels under overload conditions. In critical situations, heat sinking of these packages is required; especially if overload condi- tions must be tolerated for extended periods of time. The third approach for lower current applications is to leave the second switch emitter (miniDIP only) open. This increases switch “on” resistance by 2:1, but reduces switch current limit by 2:1 also, resulting in a net 2:1 reduction in I2R switch dissipation under current limit conditions. The fourth approach is to clamp the VC pin to a voltage less than its internal clamp level of 2V. The LT1172 switch current limit is zero at approximately 1V on the VC pin and 2A at 2V on the VC pin. Peak switch current can be externally clamped between these two levels with a diode. See AN19 for details. LT1170/LT1171/LT1172 Synchronizing The LT1170/LT1171/LT1172 can be externally synchro- nized in the frequency range of 120kHz to 160kHz. This is accomplished as shown in the accompanying figures. Synchronizing occurs when the VC pin is pulled to ground with an external transistor. To avoid disturbing the DC characteristics of the internal error amplifier, the width of the synchronizing pulse should be under 0.3 µs. C2 sets the pulse width at ≅ 0.2µs. The effect of a synchronizing pulse on the LT1170/LT1171/LT1172 amplifier offset can be calculated from: KT = 26mV at 25 °C q tS = pulse width fS = pulse frequency IC =VC source current (≈ 200µA) VC = operating VC voltage (1V to 2V) R3 = resistor used to set mid-frequency “zero” in frequency compensation network. With tS = 0.2µs, fS = 150kHz, VC = 1.5V, and R3 = 2k, offset voltage shift is ≈3.8mV. This is not particularly bother- some, but note that high offsets could result if R3 were reduced to a much lower value. Also, the synchronizing transistor must sink higher currents with low values of R3, so larger drives may have to be used. The transistor must be capable of pulling the VC pin to within 200mV of ground to ensure synchronizing. Synchronizing with MOS Transistor Synchronizing with Bipolar Transistor ∆V KT q tf I V R I OS SS C C C = ()( ) + 3 1170/1/2 OP01 C2 39pF R1 3k R2 2.2k LT1170 GND VIN VC C1 R3 2N2369 FROM 5V LOGIC 1170/1/2 OP02 D1 1N4158 R2 2.2k LT1170 GND VIN VC C1 R3 FROM 5V LOGIC C2 100pF D2 1N4158 * SILICONIX OR EQUIVALENT VN2222* OPERATIO |
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