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LT1226CS8 Datasheet(PDF) 6 Page - Linear Technology |
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LT1226CS8 Datasheet(HTML) 6 Page - Linear Technology |
6 / 8 page LT1226 6 S APPLICATI I FOR ATIO The LT1226 may be inserted directly into HA2541, HA2544, AD847, EL2020 and LM6361 applications, provided that the amplifier configuration is a noise gain of 25 or greater, and the nulling circuitry is removed. The suggested nulling circuit for the LT1226 is shown below. Offset Nulling Layout and Passive Components As with any high speed operational amplifier, care must be taken in board layout in order to obtain maximum perfor- mance. Key layout issues include: use of a ground plane, minimization of stray capacitance at the input pins, short lead lengths, RF-quality bypass capacitors located close to the device (typically 0.01 µF to 0.1µF), and use of low ESR bypass capacitors for high drive current applications (typically 1 µF to 10µF tantalum). Sockets should be avoided when maximum frequency performance is required, although low profile sockets can provide reasonable performance up to 50MHz. For more details see Design Note 50. Feedback resistors greater than 5k Ω are not recommended because a pole is formed with the input capacitance which can cause peaking. If feedback resistors greater than 5k Ω are used, a parallel capacitor of 5pF to 10pF should be used to cancel the input pole and optimize dynamic performance. Transient Response The LT1226 gain bandwidth is 1GHz when measured at 1MHz. The actual frequency response in a gain of +25 is considerably higher than 40MHz due to peaking caused by a second pole beyond the gain of 25 crossover point. This is reflected in the small signal transient response. Higher noise gain configurations exhibit less overshoot as seen in the inverting gain of 25 response. Small Signal, AV = +25 Small Signal, AV = – 25 The large signal response in both inverting and noninvert- ing gain shows symmetrical slewing characteristics. Nor- mally the noninverting response has a much faster rising edge due to the rapid change in input common mode voltage which affects the tail current of the input differen- tial pair. Slew enhancement circuitry has been added to the LT1226 so that the falling edge slew rate is enhanced which balances the noninverting slew rate response. Large Signal, AV = +25 Large Signal, AV = – 25 Input Considerations Resistors in series with the inputs are recommended for the LT1226 in applications where the differential input voltage exceeds ±6V continuously or on a transient basis. An example would be in noninverting configurations with high input slew rates or when driving heavy capacitive loads. The use of balanced source resistance at each input is recommended for applications where DC accuracy must be maximized. Capacitive Loading The LT1226 is stable with all capacitive loads. This is accomplished by sensing the load induced output pole and adding compensation at the amplifier gain node. As the capacitive load increases, both the bandwidth and phase margin decrease so there will be peaking in the LT1226 AI03 LT1226 AI02 – + 3 2 1 8 5k 0.1 µF 7 6 4 0.1 µF V+ V – LT1226 LT1226 AI01 |
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