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LT1248IN Datasheet(PDF) 8 Page - Linear Technology |
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LT1248IN Datasheet(HTML) 8 Page - Linear Technology |
8 / 12 page 8 LT1248 ripple fed back to the error amplifier is minimized. Note that switching ripple on the high impedance lines could get into the multiplier from the IAC pin and cause instability. The LT1248 provides an internal 25k resistor in series with the low impedance multiplier current input so that only a capacitor from the IAC pin to GND is needed to filter out the noise. The maximum multiplier output current, which limits the system line current, is set by the RSET according to the formula: IM(MAX) = 3.75V/RSET. Oscillator Frequency and Maximum Line Current Settling Oscillator frequency is set by RSET and CSET. Ramp ampli- tude is 5V and CSET charging current is set by VREF/RSET. Typical discharging time for CSET = 1nF is 250ns. RSET should always be determined first to set the maximum multiplier output current for system line current limit. For a 300W preregulator, with RSET = 15k, IM(MAX)=3.75V/15k = 250 µA. With a 4k resistor RREF from MOUT to the 0.2Ω line current sense resistor RS, the line current limit is: (IM • 4k)/RS. As a general rule, RS is chosen according to: RS = IM(MAX) • RREF • VLINE(MIN) K(1.414)POUT(MAX) where POUT(MAX) is the maximum power output and K is usually between 1.1 and 1.3 depending on efficiency and resistor tolerance. With RSET selected, CSET can then be determined by: CSET = 1.5/(Frequency • RSET). For 100kHz, CSET = 1.5/(100kHz • 15k) = 1nF. For optional double protection, the LT1248 provides a current limit compara- tor. When the comparator trips at 0V, the GTDR pin quickly goes low to shut off the MOS switch. A resistor divider from VREF to RS (Figure 2) senses the voltage across the line current sense resistor and the current limit is set by: ILINE = [(7.5V/R1) + 50µA](R2/RS), where 50µA is IPKLIM. S APPLICATI I FOR ATIO With ILINE and RS chosen, let R1 = 10k, then R2 = (ILINE • RS)/0.8mA. Always use RSET to set the primary line current limit. The PKLIM comparator is only for secondary protection. The secondary limit should be higher than the primary limit; 6.5A is good (5A for primary limit) for a 300W regulator. When line current reaches the primary limit, VOUT drops to keep the line current constant, and system stability is still maintained by the current loop which is controlled by the current amplifier. When line current reaches the second- ary limit, the comparator controls the system and loop hysteresis may occur and can cause audible noise. Synchronization The LT1248 can be synchronized to a frequency that is up to 1.6 times the natural frequency. With a 200ns one-shot timer on-chip, the LT1248 provides flexibility on the synchronizing pulse width. Because the EN/SYNC pin also serves the chip shutdown function, the pulses at the pin should not go below 3V and must go below 5V with widths greater than 200ns. The Figure 3 circuit will synchronize the LT1248. Figure 2 + – ILINE RS 0.2 Ω IPKLIM C1 1nF 7.5V VREF PKLIM C1 IS TO REJECT NOISE, CURRENT LIMIT DELAY IS ABOUT 2 µs. R2 1.6k R1 10k – + 1248 F02 Overvoltage Protection Because of the slow loop response necessary for power factor correction, output overshoot can occur with sudden load removal or reduction. To protect the power compo- nents and output load, the LT1248 provides an overvolt- age comparator which senses the output voltage and quickly shuts off the current switch. In Figure 4, because there is no DC current going through R3, R1 and R2 set the regulator output DC level: VOUT = VREF[(R1 + R2)/R2], with R1 = 1M, R2 = 20k, VOUT is 382V. Figure 3 30k VREF 200k VCC 1N4148 1N4685 3.6V EN/SYNC VN2222 SYNC PULSE AT LEAST 200ns 1248 F03 |
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