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LT1373IN8 Datasheet(PDF) 7 Page - Linear Technology |
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LT1373IN8 Datasheet(HTML) 7 Page - Linear Technology |
7 / 12 page 7 LT1373 Negative Output Voltage Setting The LT1373 develops a – 2.45V reference (VNFR) from the NFB pin to ground. Output voltage is set by connecting the NFB pin to an output resistor divider (Figure 2). The – 7 µA NFB pin bias current (INFB) can cause output voltage errors and should not be ignored. This has been accounted for in the formula in Figure 2. The suggested value for R2 is 2.49k. The FB pin is normally left open for negative output applications. See Dual Polarity Output Voltage Sensing for limitations of FB pin loading when using the NFB pin. A logic low on the S/S pin activates shutdown, reducing the part’s supply current to 12 µA. Typical synchronization range is from 1.05 and 1.8 times the part’s natural switch- ing frequency, but is only guaranteed between 300kHz and 340kHz. A 12 µs resetable shutdown delay network guar- antees the part will not go into shutdown while receiving a synchronization signal. Caution should be used when synchronizing above 330kHz because at higher sync frequencies the ampli- tude of the internal slope compensation used to prevent subharmonic switching is reduced. This type of subharmonic switching only occurs when the duty cycle of the switch is above 50%. Higher inductor values will tend to eliminate problems. Thermal Considerations Care should be taken to ensure that the worst-case input voltage and load current conditions do not cause exces- sive die temperatures. The packages are rated at 120 °C/W for SO (S8) and 130 °C/W for PDIP (N8). Average supply current (including driver current) is: IIN = 1mA + DC (ISW/60 + ISW • 0.004) ISW = switch current DC = switch duty cycle Switch power dissipation is given by: PSW = (ISW)2 • RSW • DC RSW = output switch “On” resistance Total power dissipation of the die is the sum of supply current times supply voltage plus switch power: PD(TOTAL) = (IIN • VIN) + PSW Choosing the Inductor For most applications the inductor will fall in the range of 10 µHto50µH.Lowervaluesarechosentoreducephysical size of the inductor. Higher values allow more output current because they reduce peak current seen by the power switch which has a 1.5A limit. Higher values also reduce input ripple voltage, and reduce core loss. When choosing an inductor you might have to consider maximum load current, core and copper losses, allowable R1 –VOUT = VNFB + INFB (R1) 1 + R2 LT1373 • F02 NFB PIN VNFR INFB –VOUT ()R1 R2 R1 = + (7 • 10–6) VOUT – 2.45 () 2.45 R2 Figure 2. Negative Output Resistor Divider Dual Polarity Output Voltage Sensing Certain applications benefit from sensing both positive and negative output voltages. One example is the Dual Output Flyback Converter with Overvoltage Protection circuit shown in the Typical Applications section. Each output voltage resistor divider is individually set as de- scribed above. When both the FB and NFB pins are used, the LT1373 acts to prevent either output from going beyond its set output voltage. For example in this applica- tion, if the positive output were more heavily loaded than the negative, the negative output would be greater and would regulate at the desired set-point voltage. The posi- tive output would sag slightly below its set-point voltage. This technique prevents either output from going unregu- lated high at no load. Please note that the load on the FB pin should not exceed 100 µA when the NFB pin is used. This situation occurs when the resistor dividers are used at both FB and NFB. True load on FB is not the full divider current unless the positive output is shorted to ground. See Dual Output Flyback Converter application. Shutdown and Synchronization The dual function S/S pin provides easy shutdown and synchronization. It is logic level compatible and can be pulled high, tied to VIN or left floating for normal operation. APPLICATIO S I FOR ATIO |
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