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LTC3717 Datasheet(PDF) 9 Page - Linear Technology

Part # LTC3717
Description  Wide Operating Range, No RSENSE Step-Down Controller for DDR/QDR Memory Termination
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC3717 Datasheet(HTML) 9 Page - Linear Technology

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LTC3717
sn3717 3717fs
APPLICATIO S I FOR ATIO
the load current. During LTC3717’s normal operation, the
duty cycles for the MOSFETs are:
D
V
V
D
VV
V
TOP
OUT
IN
BOT
IN
OUT
IN
=
=
The resulting power dissipation in the MOSFETs at maxi-
mum output current are:
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
Both MOSFETs have I2R losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
JUNCTION TEMPERATURE (
°C)
–50
1.0
1.5
150
3717 F02
0.5
0
0
50
100
2.0
Figure 2. RDS(ON) vs. Temperature
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3717 applications is deter-
mined implicitly by the one-shot timer that controls the
the LTC3717 and external component values and a good
guide for selecting the sense resistance is:
R
V
I
SENSE
RNG
OUT MAX
=
10 •
()
An external resistive divider from INTVCC can be used to set
the voltage of the VRNG pin between 0.5V and 2V resulting
in nominal sense voltages of 50mV to 200mV. Additionally,
the VRNG pin can be tied to SGND or INTVCC in which case
the nominal sense voltage defaults to 70mV or 140mV,
respectively. The maximum allowed sense voltage is about
1.3 times this nominal value for positive output current and
1.7 times the nominal value for negative output current.
Power MOSFET Selection
The LTC3717 requires two external N-channel power MOS-
FETs, one for the top (main) switch and one for the bottom
(synchronous) switch. Important parameters for the power
MOSFETs are the breakdown voltage V(BR)DSS, threshold
voltage V(GS)TH, on-resistance RDS(ON), reverse transfer
capacitance CRSS and maximum current IDS(MAX).
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3717 applications. If the input voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its on-
resistance. MOSFET on-resistance is typically specified
with a maximum value RDS(ON)(MAX) at 25°C. In this case,
additional margin is required to accommodate the rise in
MOSFET on-resistance with temperature:
R
R
DS ON MAX
SENSE
T
()(
) =
ρ
The
ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/
°C as shown in
Figure 2. For a maximum junction temperature of 100
°C,
using a value
ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and


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