11

LT1813

Example: LT1813 in SO-8 at 70

Circuit Operation

The LT1813 circuit topology is a true voltage feedback

amplifier that has the slewing behavior of a current feed-

back amplifier. The operation of the circuit can be under-

stood by referring to the Simplified Schematic. The inputs

are buffered by complementary NPN and PNP emitter

followers which drive a 300

Ω resistor. The input voltage

appears across the resistor generating currents that are

mirrored into the high impedance node.

Complementary followers form an output stage that buff-

ers the gain node from the load. The bandwidth is set by

the input resistor and the capacitance on the high imped-

ance node. The slew rate is determined by the current

available to charge the gain node capacitance. This current

is the differential input voltage divided by R1, so the slew

rate is proportional to the input. Highest slew rates are

therefore seen in the lowest gain configurations.

The RC network across the output stage is bootstrapped

when the amplifier is driving a light or moderate load and

has no effect under normal operation. When driving ca-

pacitive loads (or a low value resistive load) the network is

incompletely bootstrapped and adds to the compensation

at the high impedance node. The added capacitance slows

down the amplifier which improves the phase margin by

moving the unity-gain cross away from the pole formed by

the output impedance and the capacitive load. The zero

created by the RC combination adds phase to ensure that

the total phase lag does not exceed 180 degrees (zero

phase margin) and the amplifier remains stable. In this

way, the LT1813 is stable with up to 1000pF capacitive

loads in unity gain, and even higher capacitive loads in

higher closed-loop gain configurations.

1813 SS

OUT

+IN

–IN

R1

300

Ω

C

SI PLIFIED

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.