LTC2351-14

1

235114fb

FEATURES

APPLICATIONS

DESCRIPTION

6-Channel, 14-Bit, 1.5Msps

Simultaneous Sampling ADC

with Shutdown

taneously sampled differential inputs. The device draws

only 5.5mA from a single 3V supply, and comes in a tiny

32-pin (5mm

× 5mm) QFN package. A sleep shutdown

mode further reduces power consumption to 12μW. The

combination of low power and tiny package makes the

LTC2351-14 suitable for portable applications.

The LTC2351-14 contains six separate differential inputs

that are sampled simultaneously on the rising edge of the

CONV signal. These six sampled inputs are then converted

at a rate of 250ksps per channel.

The 83dB common mode rejection allows users to eliminate

ground loops and common mode noise by measuring

signals differentially from the source.

The device converts 0V to 2.5V unipolar inputs differentially,

or ±1.25V bipolar inputs also differentially, depending on the

state of the BIP pin. Any analog input may swing rail-to-rail

as long as the differential input range is maintained.

The conversion sequence can be abbreviated to convert

fewer than six channels, depending on the logic state of

the SEL2, SEL1 and SEL0 inputs.

Theserialinterfacesendsoutthesixconversionresultsin96

clocks for compatibility with standard serial interfaces.

Differential Inputs

with External Reference

Input Range

× 5mm) QFN Package

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents,

including 6084440, 6522187.

BLOCK DIAGRAM

–

4

5

25

24

–

7

6

9

12

13

16

19

8

10

11

–

14

15

–

17

18

–

20

21

S AND H

S AND H

S AND H

S AND H

S AND H

MUX

10μF

BIP

SEL2 SEL1 SEL0

GND

2.5V

REFERENCE

1.5Msps

14-BIT ADC

14-BIT LATCH 5

14-BIT LATCH 4

14-BIT LATCH 3

14-BIT LATCH 2

14-BIT LATCH 1

14-BIT LATCH 0

10μF

3V

26

29

23

22

33

27

28

2

1

SD0

0.1μF

3

3V

32

SCK

31

DGND

OGND

30

CONV

THREE-

STATE

SERIAL

OUTPUT

PORT

TIMING

LOGIC

235114 TA01

–

S AND H