LTC3527/LTC3527-1

3

35271fc

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3527E/LTC3527E-1 are guaranteed to meet performance

specifications from 0°C to 85°C. Specifications over the –40°C to 85°C

operating temperature range are assured by design, characterization and

correlation with statistical process controls.

bootstrapped to the output. The current will reflect to the input supply by:

The

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PMOS Switch Leakage Current (LTC3527)

0.1

10

μA

NMOS and PMOS Combined Switch Leakage Current

(LTC3527-1)

0.2

20

μA

NMOS Switch On-Resistance, SW1

0.30

Ω

NMOS Switch On-Resistance, SW2

0.50

Ω

PMOS Switch On-Resistance, SW1

0.40

Ω

PMOS Switch On-Resistance, SW2

0.60

Ω

NMOS Current Limit, SW1

l

800

mA

NMOS Current Limit, SW2

l

400

mA

Current Limit Delay to Output Time

(Note 4)

60

ns

Maximum Duty Cycle

l

85

90

%

Minimum Duty Cycle

l

0%

Switching Frequency

l

0.9

1.2

1.5

MHz

Switching Frequency

l

1.8

2.2

2.8

MHz

SHDN1,2 Input High Voltage

0.88

V

SHDN1,2 Input Low Voltage

0.35

V

SHDN1,2 Input Current

1

2

μA

PGOOD1, PGOOD2 Threshold

Referenced to the Feedback Voltage

–6

–9

–14

%

PGOOD1, PGOOD2 Low Voltage

0.1

0.2

V

PGOOD1, PGOOD2 Leakage Current

0.01

1

μA

MODE Input High Voltage

1V

MODE Input Low Voltage

0.35

V

MODE Input Current

1

2

μA

FSEL Input High Voltage

0.88

V

FSEL Input Low Voltage

0.35

V

FSEL Input Current

1

2

μA

Soft-Start Time

0.5

ms

Note 4: Specification is guaranteed by design and not 100% tested in

production.

Note 5: The LTC3527/LTC3527-1 includes an overtemperature shutdown

that is intended to protect the device during momentary overload

conditions. Junction temperature will exceed 125°C when the over-

temperature shutdown is active. Continuous operation above the specified

maximum junction temperature may impair device reliability.

Note 6: The NMOS and PMOS switch leakage currents are tested in parallel

SHDN1,2 = 0V