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LTC1064-7M Datasheet(PDF) 11 Page - Linear Technology |
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LTC1064-7M Datasheet(HTML) 11 Page - Linear Technology |
11 / 12 page 11 LTC1064-7 S APPLICATI I FOR ATIO Speed Limitations To avoid op amp slew rate limiting at maximum clock frequencies, the signal amplitude should be kept below a specified level as shown in Table 9. Table 9. Maximum VIN vs VS and Clock POWER SUPPLY MAXIMUM fCLK MAXIMUM VIN ±7.5V 5.0MHz 1.8VRMS (fIN > 80kHz) 4.5MHz 2.3VRMS (fIN > 80kHz) 4.0MHz 2.7VRMS (fIN > 80kHz) ≥ 3.5MHz 1.4VRMS (fIN > 500kHz) ±5V 3.5MHz 1.6VRMS (fIN > 80kHz) ≥ 3.0MHz 0.7VRMS (fIN > 400kHz) Single 5V 2.0MHz 0.5VRMS (fIN > 250kHz) Table 10. Transient Response of LTC Lowpass Filters DELAY RISE SETTLING OVER- TIME* TIME** TIME*** SHOOT LOWPASS FILTER (SEC) (SEC) (SEC) (%) LTC1064-3 Bessel 0.50/fC 0.34/fC 0.80/fC 0.5 LTC1164-5 Bessel 0.43/fC 0.34/fC 0.85/fC 0 LTC1164-6 Bessel 0.43/fC 0.34/fC 1.15/fC 1 LTC1264-7 Linear Phase 1.15/fC 0.36/fC 2.05/fC 5 LTC1164-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC 5 LTC1064-7 Linear Phase 1.20/fC 0.39/fC 2.2/fC 5 LTC1164-5 Butterworth 0.80/fC 0.48/fC 2.4/fC 11 LTC1164-6 Elliptic 0.85/fC 0.54/fC 4.3/fC 18 LTC1064-4 Elliptic 0.90/fC 0.54/fC 4.5/fC 20 LTC1064-1 Elliptic 0.85/fC 0.54/fC 6.5/fC 20 * To 50% ±5%, ** 10% to 90% ±5%, *** To 1% ±0.5% Table 11. Aliasing (fCLK = 100kHz) INPUT FREQUENCY OUTPUT LEVEL OUTPUT FREQUENCY (VIN = 1VRMS, (Relative to Input, (Aliased Frequency fIN = fCLK ± fOUT) 0dB = 1VRMS)fOUT = ABS [fCLK ± fIN]) (kHz) (dB) (kHz) 50:1, fCUTOFF = 2kHz 190 (or 210) –76.1 10.0 195 (or 205) – 51.9 5.0 196 (or 204) – 36.3 4.0 197 (or 203) – 18.4 3.0 198 (or 202) – 3.0 2.0 199.5 (or 200.5) – 0.2 0.5 100:1, fCUTOFF = 1kHz 97 (or 103) –74.2 3.0 97.5 (or 102.5) – 53.2 2.5 98 (or 102) – 36.9 2.0 98.5 (or 101.5) – 19.6 1.5 99 (or 101) – 5.2 1.0 99.5 (or 100.5) – 0.7 0.5 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. Transient Response 50 µs/DIV 1064-7 F05 VS = ±7.5V, fIN = 2kHz ± 3V fCLK = 1MHz, RATIO = 50:1 Figure 6. INPUT 90% 50% 10% OUTPUT tr td ts 1064-7 F06 RISE TIME (tr) = ±5% 0.39 fCUTOFF SETTLING TIME (ts) = ±5% (TO 1% of OUTPUT) 2.2 fCUTOFF DELAY TIME (td) = GROUP DELAY ≈ (TO 50% OF OUTPUT) 1.2 fCUTOFF Figure 5. Aliasing Aliasing is an inherent phenomenon of sampled data systems and it occurs when input frequencies close to the sampling frequency are applied. For the LTC1064-7 case at 100:1, an input signal whose frequency is in the range of fCLK ±3%, will be aliased back into the filter’s passband. If, for instance, an LTC1064-7 operating with a 100kHz clock and 1kHz cutoff frequency receives a 98kHz, 10mV input signal, a 2kHz, 143 µVRMS alias signal will appear at its output. When the LTC1064-7 operates with a clock-to- cutoff frequency of 50:1, aliasing occurs at twice the clock frequency. Table 11 shows details. |
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