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LTC1289CC Datasheet(PDF) 9 Page - Linear Technology |
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LTC1289CC Datasheet(HTML) 9 Page - Linear Technology |
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9 / 28 page  9 LTC1289 S APPLICATI I FOR ATIO previous conversion is output on the DOUT line. At the end of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one CS cycle from the input word requesting it. Operating Sequence (Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length) Input Data Word The LTC1289 8-bit data word is clocked into the DIN input on the first eight rising SCLK edges after chip select is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input word are defined as follows: DIN DOUT DOUT WORD 0 DIN WORD 1 DATA TRANSFER DOUT WORD 2 DIN WORD 3 DOUT WORD 1 DIN WORD 2 DATA TRANSFER tCONV A/D CONVERSION tCONV A/D CONVERSION LTC1289 AI01 SGL/ DIFF SELECT 1 SELECT 0 UNI MSBF WL1 MUX ADDRESS MSB-FIRST/ LSB-FIRST UNIPOLAR/ BIPOLAR WORD LENGTH LTC1289 AI02 ODD/ SIGN WL0 123456789 10 11 12 tCONV DON'T CARE DON'T CARE tCYC SHIFT CONFIGURATION WORD IN tSMPL SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (SB) LTC1289 AI03 SCLK DIN DOUT CS The LTC1289 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample and hold (S/H) 4. Synchronous, full duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface The LTC1289 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four wire serial interface (see Operating Sequence). The shift clock (SCLK) synchronizes the data transfer with each bit being transmitted on the falling SCLK edge and captured on the rising SCLK edge in both transmitting and receiving systems. The data is transmitted and received simulta- neously (full duplex). Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 8-bit input word is shifted into the DIN input which configures the LTC1289 for the next conversion. Simultaneously, the result of the |
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