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LTC1291DIJ8 Datasheet(PDF) 3 Page - Linear Technology |
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LTC1291DIJ8 Datasheet(HTML) 3 Page - Linear Technology |
3 / 20 page 3 LTC1291 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS tdis Delay Time, CS ↑ to DOUT Hi-Z See Test Circuits q 80 150 ns ten Delay Time, CLK ↓ to DOUT Enabled See Test Circuits q 80 200 ns thDI Hold Time, DIN after CLK ↑ VCC = 5V (Note 6) 50 ns thDO Time Output Data Remains Valid after CLK ↓ 130 ns tWHCLK CLK High Time VCC = 5V (Note 6) 300 ns tWLCLK CLK Low Time VCC = 5V (Note 6) 400 ns tf DOUT Fall Time See Test Circuits q 65 130 ns tr DOUT Rise Time See Test Circuits q 25 50 ns tsuDI Setup Time, DIN Stable before CLK ↑ VCC = 5V (Note 6) 50 ns tsuCS Setup Time, CS ↓ before CLK↑ VCC = 5V (Note 6) 50 ns tWHCS CS High Time During Conversion VCC = 5V (Note 6) 500 ns tWLCS CS Low Time During Data Transfer VCC = 5V (Note 6) 18 CLK Cycles CIN Input Capacitance Analog Inputs On Channel 100 pF Analog Inputs Off Channel 5 pF Digital Inputs 5 pF AC CHARACTERISTICS (Note 3) Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct, especially at elevated temperature, and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. Note 8: Channel leakage current is measured after the channel selection. Note 9: Increased leakage currents at elevated temperatures cause the S/H to droop, therefore it is recommended that fCLK ≥ 125kHz at 125°C, fCLK ≥ 30kHz at 85°C and fCLK ≥ 3kHz at 25°C. The q denotes specifications which apply over the operating temperature range; all other limits and typicals TA = 25 °C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground (unless otherwise noted). Note 3: VCC = 5V, CLK = 1.0MHz unless otherwise specified. Note 4: One LSB is equal to VCC divided by 4096. For example, when VCC = 5V, 1LSB = 5V/4096 = 1.22mV. Note 5: Linearity error is specified between the actual end points of the A/D transfer curve. The deviation is measured from the center of the quantization band. Note 6: Recommended operating conditions. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIH High Level Input Voltage VCC = 5.25V q 2.0 V VIL Low Level Input Voltage VCC = 4.75V q 0.8 V IIH High Level Input Current VIN = VCC q 2.5 µA IIL Low Level Input Current VIN = 0V q –2.5 µA VOH High Level Output Voltage VCC = 4.75V, IOUT = –10 µA 4.7 V VCC = 4.75V, IOUT = – 360 µA q 2.4 4.0 V VOL Low Level Output Voltage VCC = 4.75V, IOUT = 1.6mA q 0.4 V IOZ High Z Output Leakage VOUT = VCC, CS High q 3 µA VOUT = 0V, CS High q –3 µA ISOURCE Output Source Current VOUT = 0V – 20 mA ISINK Output Sink Current VOUT = VCC 20 mA ICC Positive Supply Current CS High q 612 mA LTC1291BC, LTC1291CC, LTC1291DC q 510 µA LTC1291BI, LTC1291CI, LTC1291DI, q 515 µA LTC1291BM, LTC1291CM, LTC1291DM LTC1291B/LTC1291C/LTC1291D (Note 3) ELECTRICAL C C HARA TER STICS DIGITAL A D I DC LTC1291B/LTC1291C/LTC1291D CS High Power shutdown CLK Off |
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Similar Description - LTC1291DIJ8 |
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