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TESDC5V0RRG Datasheet(PDF) 3 Page - Taiwan Semiconductor Company, Ltd |
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TESDC5V0RRG Datasheet(HTML) 3 Page - Taiwan Semiconductor Company, Ltd |
3 / 4 page PACKAGE OUTLINE DIMENSIONS Min Max Min Max A 1.150 1.400 0.045 0.055 B 2.300 2.700 0.091 0.106 C 0.250 0.450 0.010 0.018 D 1.600 1.800 0.063 0.071 E 0.800 1.000 0.031 0.039 F 0.050 0.177 0.002 0.007 G H - 0.100 - 0.004 SUGGEST PAD LAYOUT G X X1 Y Note: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary depending on application. APPLICATION INFROMATION - Designed to protect one data, I/O, or power supply line - Designed to protect sensitive electronics from damage or latch-up due to ESD - Designed to replace multilayer varistors (MLVs) in portable applications - Offers superior electrical characteristics such as lower clamping voltage and no device degradation when compared to MLVs - The combination of small size and high ESD surge capability makes them ideal for use in portable applications CIRCUIT BOARD LAYOUT RECOMMENDATIONS - Good circuit board layout is critical for the suppression of ESD induced transients - Place the ESD Protection Diode near the input terminals or connectors to restrict transient coupling - Minimize the path length between the ESD Protection Diode and the protected line - Minimize all conductive loops including power and ground loops - The ESD transient return path to ground should be kept as short as possible Document Number: DS_S1501013 Version: C15 TESDC5V0 Taiwan Semiconductor Small Signal Product ORDER INFORMATION (EXAMPLE) SOD-323 DIM. Unit (mm) Unit (inch) 0.475 REF 0.019 REF DIM. Unit (mm) Unit (inch) Min Min 0.45 0.018 1.52 0.060 0.59 0.023 2.70 0.106 TESDC5V0 RRG Green compound code Packing code Part no. B A E D C F G H |
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