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LTC1402 Datasheet(PDF) 4 Page - Linear Technology |
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LTC1402 Datasheet(HTML) 4 Page - Linear Technology |
4 / 20 page 4 LTC1402 SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS fSAMPLE(MAX) Maximum Sampling Frequency (Conversion Rate) q 2.2 MHz tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) q 455 ns tSCK Minimum Clock Period q 28 10000 ns tCONV Conversion Time Greater Than 13 Clocks + 6ns (Note 9) q 375 ns tACQ Acquisition Time Greater Than 2 Clocks – 6ns (Notes 9, 16) q 51 ns t1 Minimum Positive or Negative SCK Pulse Width (Note 9) q 3.8 6 ns t2 CONV to SCK Setup Time (Notes 9, 13) q 7.3 12 ns t3 SCK After CONV (Note 9) q 0ns t4 Minimum Positive or Negative CONV Pulse Width (Note 9) q 3.5 5 ns t5 SCK to Sample Mode (Notes 9, 14) q 914 ns t6 CONV to Hold Mode (Note 9) q 3.4 5 ns t7 Minimum Delay Between Conversions (Note 9) q 48 ns t8 Minimum Delay from SCK to Valid Bits 0 Through 11 (Notes 9, 15) q 912 ns t8a Minimum Delay from SCK to Valid REFREADY (Notes 9, 15) q 15 20 ns t9 SCK to Hi-Z at DOUT (Notes 9, 15) q 11.4 16 ns t10 Previous DOUT Bit Remains Valid After SCK (Notes 9, 15) q 47 ns t11 REFREADY Bit Delay After Sleep-to-Wake Transition (Notes 9, 17) q 10 ms t12 VREF Settling Time After Sleep-to-Wake Transition (Notes 9, 17) q 2ms The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD Positive Supply Voltage 4.75 5.00 5.25 V VSS Negative Supply Voltage – 5.25 – 5.00 0 V IDD Positive Supply Current Active Mode q 18 30 mA Nap Mode q 35 mA Sleep Mode 2 10 µA ISS Negative Supply Current Active, Sleep or Nap Modes with SCK Off q 2 µA PD Power Dissipation Active Mode with SCK in Fixed State (Hi or Lo) 90 150 mW POWER REQUIRE E TS Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND, AGND1 and AGND2 wired together. Note 3: When these pins are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or greater than VDD without latchup. Note 4: When these pins are taken below VSS, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS or greater than VDD. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 2.2MHz, VSS = 0V for unipolar mode specifications and VSS = – 5V for bipolar specifications. The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) Note 6: Linearity, offset and full-scale specifications apply for a single- ended AIN + input with AIN– grounded and using the internal reference in bipolar mode with ±5V supplies. Note 7: Integral linearity is defined as the deviation of a code from the straight line passing through the actual endpoints of a transfer curve. The deviation is measured from the center of quantization band. Note 8: Bipolar offset is the offset measured from – 0.5LSB when the input flickers between 1000 0000 0000 and 0111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The analog input range is defined as the voltage difference between AIN + and AIN–. The bipolar ±2.048V input range could be used with a single 5V supply if the absolute voltages of the inputs remain within the single 5V supply voltage. TI I G CHARACTERISTICS |
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