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UPD75P116 Datasheet(PDF) 8 Page - NEC |
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UPD75P116 Datasheet(HTML) 8 Page - NEC |
8 / 32 page 8 µPD75P116 1.2 OTHER PINS Dual- Function Pin — — P20 P21 P01 P02 P03 P00 P10 P11 P12 P13 P22 — — P30 to P33 — — — I/O Circuit Type *1 N B E F E B B B B E B E Pin Name PTH00 to PTH03 TI0 TI1 PTO0 PTO1 SCK SO SI INT4 INT0 INT1 INT2 INT3 PCL X1, X2 RESET MD0 to MD3 VDD VSS VPP *2 Input/Output Input Input Input/output Input/output Input/output Input Input Input Input Input/output Input Input/output Function Variable threshold voltage 4-bit analog input port. External event pulse input to timer/event counter. Or edge detection vectored interrupt input pin, or 1-bit input is also possible. Timer/event counter output pin. Serial clock input/output pin. Serial data output pin. Serial data input pin. Edge detection vector interrupt input pin (detection of both rising and falling edges). Edge detection vector interrupt input pin (detection edge selectable). Edge detection testable input pin (rising edge detection) Clock output pin System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. System reset input pin (low-level active). Mode selection pin for program memory (PROM) write/ verify. Positive power supply pin. Applies +6 V for write/verify. GND potential pin. Program voltage impression pin for program memory (PROM) write/verify. Connected to VDD directly in normal operation. Applies +12.5 V for PROM write/verify. After Reset Input Input Input Input Input Input *1. indicates Schmitt-triggered input. 2. The device will not operate correctly unless VPP is connected to VDD directly in normal use. |
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