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LTC1405IGN Datasheet(PDF) 7 Page - Linear Technology |
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LTC1405IGN Datasheet(HTML) 7 Page - Linear Technology |
7 / 16 page 7 LTC1405 Conversion Details The LTC1405 is a high performance 12-bit A/D converter that operates up to 5Msps. It is a complete solution with an on-chip sample-and-hold, a 12-bit pipelined CMOS ADC, a low drift programmable reference and an input programmable gain amplifier. The digital output is paral- lel, with a 12-bit two’s complement output and an out-of- range (overflow) bit. The rising edge of the CLK begins a conversion. The differential analog inputs are simultaneously sampled and passed on to the pipelined A/D. After two more conversion starts (plus a 150ns conversion time) the digital outputs are updated with the conversion result and will be ready for capture on the third rising clock edge. Thus even though a new conversion is begun every time CLK goes high, each result takes three clock cycles to reach the output. The analog signals that are passed from stage to stage in the pipelined A/D are stored on capacitors. The signals on these capacitors will be lost if the delay between conver- sions is too long. For accurate conversion results, the part should be clocked faster than 20kHz. In some pipelined A/D converters if there is no clock present, dynamic logic on the chip will droop and the power consumption sharply increases. The LTC1405 doesn’t have this problem. If the part is not clocked for 1ms, an internal timer will refresh the dynamic logic. Thus the clock can be turned off for long periods of time to save power. Power Supplies The LTC1405 will operate from either a single 5V or dual ±5V supply, making it easy to interface the analog input to single or dual supply systems. The digital output drivers have their own power supply pin (OVDD) which can be set from 3V to 5V, allowing direct connection to either 3V or 5V digital systems. For single supply operation, VSS should be connected to analog ground. For dual supply operation, VSS should be connected to – 5V. Both VDD pins should be connected to a clean 5V analog supply. (Don’t connect VDD to a noisy system digital supply.) APPLICATIO S I FOR ATIO Analog Input Ranges The LTC1405 has a flexible analog input with a wide selection of input ranges. The input range is always differential and is set by the voltages at the VREF and the GAIN pins (Figure 1). The input range of the A/D core is fixed at ±VREF/2. The reference voltage, VREF, is either set by the on-chip voltage reference or directly driven by an external voltage. The GAIN pin is a digital input that controls the gain of a preamplifier in the sample-and-hold circuit. The gain of this PGA can be set to 1x or 2x. Table 1 gives the input range in terms of VREF and GAIN. Table 1 INPUT RANGE GAIN PIN PGA GAIN (VIN = AIN+ – AIN–) 5V (Logic H) 1x – VREF/2 < VIN < VREF/2 OV (Logic L) 2x – VREF/4 < VIN < VREF/4 VREF –AIN +AIN GAIN 1405 F01 1x/2x VIN + – ±VREF/2 PGA S/H ADC CORE Internal Reference Figure 2 shows a simplified schematic of the LTC1405 reference circuitry. An on-chip temperature compensated bandgap reference (VCM) is factory trimmed to 2.500V. The voltage at the VREF pin sets the input span of the ADC to ±VREF/2. An internal voltage divider converts VCM to 2.048V, which is connected to a reference amplifier. The reference programming pin, SENSE, controls how the reference amplifier drives the VREF pin. If SENSE is tied to ground, the reference amplifier feedback is connected to the R1/R2 voltage divider, thus making VREF = 4.096V. If SENSE is tied to VREF, the reference amplifier feedback is connected to SENSE thus making VREF = 2.048V. If SENSE is tied to VDD, the reference amplifier is disconnected from VREF and VREF can be driven by an external voltage. With two additional resistors, VREF can be set to any voltage between 2.048V and 4.5V. Figure 1. Analog Input Circuit |
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