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LTC1409ISW Datasheet(PDF) 7 Page - Linear Technology

Part # LTC1409ISW
Description  12-Bit, 800ksps Sampling A/D Converter with Shutdown
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC1409ISW Datasheet(HTML) 7 Page - Linear Technology

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7
LTC1409
PI FU CTIO S
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
VSS (Pin 26): – 5V Negative Supply. Bypass to AGND
using 10
µF tantalum in parallel 0.1µF or 10µF ceramic.
OVDD (Pin 27): Positive Supply for Output Drivers. For
5V logic, short to Pin 28. For 3V logic, short to supply
of the logic being driven.
AVDD (Pin 28): 5V Positive Supply. Bypass to AGND
10
µF tantalum in parallel with 0.1µF or 10µF ceramic.
Load Circuits for Bus Relinquish Time
Load Circuits for Access Timing
1k
100pF
100pF
DBN
DBN
1k
5V
LTC1409 • TC02
1k
CL
CL
DBN
DBN
1k
5V
LTC1409 • TC01
(a) Hi-Z to VOH
and VOL to VOH
(b) Hi-Z to VOL
and VOH to VOL
(a) VOH to Hi-Z
(b) VOL to Hi-Z
FU CTIO AL BLOCK DIAGRA
12-BIT CAPACITIVE DAC
COMP
REF AMP
2.5V REF
4k
REFCOMP
(4.06V)
CSAMPLE
CSAMPLE
•
•
•
D11
D0
BUSY
CONTROL LOGIC
CS
CONVST
RD
SHDN
INTERNAL
CLOCK
NAP/SLP
ZEROING SWITCHES
OVDD
OGND
AVDD
+AIN
–AIN
VREF
AGND
DGND
12
LTC1409 • BD
+
–
SUCCESSIVE APPROXIMATION
REGISTER
OUTPUT LATCHES
TEST CIRCUITS


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