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LTC1598IG Datasheet(PDF) 11 Page - Linear Technology |
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LTC1598IG Datasheet(HTML) 11 Page - Linear Technology |
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11 / 24 page  11 LTC1594/LTC1598 15948fb APPLICATIONS INFORMATION Figure 2. LTC1594/LTC1598 Operating Sequence Example: All Channels Off CLK EN D1 D2 tCYC Hi-Z DOUT CH0 TO CH7 DIN tCONV Hi-Z tsuCS NULL BIT D0 tOFF D0N‘T CARE ADCIN = MUXOUT COM = GND 1594/98 F02 DUMMY CONVERSION CSMUX = CSADC = CS break-before-make interval, tOPEN. After a delay of tON (tOFF + tOPEN), the selected channel is switched on, allowing the ADC in the chip to acquire input signal and start the conversion (see Figures 1 and 2). After 1 null bit, the result of the conversion is output on the DOUT line. The selected channel remains on, until the next falling edge of CS. At the end of the data exchange CS should be brought high. This resets the LTC1594/LTC1598 and initiates the next data exchange. DIN1 DIN2 DOUT1 DOUT2 CS SHIFT MUX ADDRESS IN tSMPL + 1 NULL BIT SHIFT A/D CONVERSION RESULT OUT 1594/98 AI01 Break-Before-Make The LTC1594/LTC1598 provide a break-before-make interval from switching off all the channels simulta- neously to switching on the next selected channel once CS is pulled low. In other words, once CS is pulled low, Data Transfer The CLK synchronizes the data transfer with each bit being transmitted on the falling CLK edge and captured on the rising CLK edge in both transmitting and receiving systems. The LTC1594/LTC1598 first receive input data and then transmit back the A/D conversion results (half duplex). Because of the half duplex operation, DIN and DOUT may be tied together allowing transmission over just 3 wires: CS, CLK and DATA (DIN/DOUT). Data transfer is initiated by a rising chip select (CS) signal. After CS rises the input data on the DIN pin is latched into a 4-bit register on the rising edge of the clock. More than four input bits can be sent to the DIN pin without problems, but only the last four bits clocked in before CS falls will be stored into the 4-bit register. This 4-bit input data word will select the channel in the multiplexer (see Input Data Word and Tables 1 and 2). To ensure correct operation the CS must be pulled low before the next rising edge of the clock. Once the CS is pulled low, all channels are simulta- neously switched off after a delay of tOFF to ensure a |
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