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LTC1647-2IS8 Datasheet(PDF) 10 Page - Linear Technology |
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LTC1647-2IS8 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 20 page  LTC1647-1/LTC1647-2/LTC1647-3 10 The circuit breaker trip voltage has a tolerance of 20%; combined with a 5% sense resistor, the total tolerance is 25%. Therefore, calculate R1 based on a trip current ITRIP of no less than 125% of the maximum operating current. Do not neglect the effect of ripple current, which adds to the maximum DC component of the load current. Ripple current may arise from any of several sources, but the worst offenders are switching supplies. A switching regulator on the load side will attempt to draw some ripple current from the backplane and this current passes through the sense resistor. Similarly, output ripple from a switching regulator supplying the backplane will flow through the sense resistor and into the load capacitor. Minimize the effects of ripple current by either filtering the VOUT line or adding an RC filter to the SENSE pin. A series inductance of 1 µHto10µHinsertedbetweenQ1andCLOAD is adequate ripple current suppression in most cases. Alternatively, a filter, consisting of R3 and C3(Figure 3), simply filters the ripple component from the SENSE pin at the expense of response time. The added delay is given by tDELAY = – R3•C3•ln[1 – (VCB/R1 – IAV)/(IPK – IAV)] Power MOSFET Selection Power MOSFETs are classified into two catagories: stan- dard MOSFETs (RDS(ON) specified at VGS = 10V) and logic- level MOSFETs (RDS(ON) specified at VGS = 5V). The absolute maximum rating for VGS is typically 20V for standard MOSFETs. The maximum rating for logic-level MOSFETs is lower and ranges from 8V to 16V depending on the manufacturer and specific part number. Some logic-level MOSFETs have a 20V maximum VGS rating. The LTC1647 is primarily targeted for standard MOSFETs; low supply voltage applications should use logic-level MOSFETs. GATE overdrive as a function of VCC is illus- trated in the Typical Performance Curves. If lower GATE overdrive is desired, connect a diode in series with a Zener between GATE and VCC or between GATE and VOUT as shown in Figure 4. The RDS(ON) of the external pass transistor must be low to make VDS a small percentage of VCC. At VCC = 3.3V, VDS + VCB = 0.1V yields 3% error at maximum load current. This restricts the choice of MOSFETs to very low RDS(ON). At higher VCC voltages, the RDS(ON) requirement can be relaxed. MOSFET package dissipation (PD and TJ) may restrict the value of RDS(ON). Figure 1. Supply Control Circuitry Figure 2. Current Fault Timing Figure 3. Filtering Current Ripple/Glitches Figure 4. Optional Gate Clamp APPLICATIO S I FOR ATIO SENSE 15 13 ON1 2 FAULT ON VCC VOUT FAULT 3 GND 8 GATE LTC1647-3 C1 10nF 1647-1/2/3 F01 R2 10 Ω R1 0.01 Ω Q1 IRF7413 CLOAD + VCC 1 R3 10k tFAULT tRESET VON VCC – VSENSE VGATE VFAULT 1647-1/2/3 F02 SENSE VCC VOUT GATE LTC1647 C1 10nF C3 10nF 1647-1/2/3 F03 R2 10 Ω R1 0.01 Ω Q1 IRF7413 CLOAD IPK = 7.5A IAV = 2.5A ITRIP = VCB/R1 = 5A tDELAY = 10µs + VCC R3 1.5k VCC VOUT *USER SELECTED VOLTAGE CLAMP 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET 1647-1/2/3 F04 R1 D1* D2 1N4148 D4* D2 1N4148 Q1 |
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