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LTC1873 Datasheet(PDF) 10 Page - Linear Technology |
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LTC1873 Datasheet(HTML) 10 Page - Linear Technology |
10 / 32 page 10 LTC1873 Switching Architecture Each half of the LTC1873 is designed to operate as a synchronous buck converter (Figure 1). Each channel includes two high power MOSFET gate drivers to control external N-channel MOSFETs QT and QB. These drivers have 0.5 Ω output impedances and can carry well over an amp of continuous current with peak currents up to 5A to slew large MOSFET gates quickly. The external MOSFETs are connected with the drain of QT attached to the input supply and the source of QT at the switching node SW. QB is the synchronous rectifier with its drain at SW and its source at PGND. SW is connected to one end of the inductor, with the other end connected to VOUT. The output capacitor is connected from VOUT to PGND. When a switching cycle begins, QB is turned off and QT is turned on. SW rises almost immediately to VIN and the inductor current begins to increase. When the PWM pulse finishes, QT turns off and one nonoverlap interval later, QB turns on. Now SW drops to PGND and the inductor current decreases. The cycle repeats with the next tick of the master clock. The percentage of time spent in each mode is controlled by the duty cycle of the PWM signal, which in turn is controlled by the feedback amplifier. The master clock runs at a 550kHz rate and turns QT once every 1.8 µs. In a typical application with a 5V input and a 1.5V output, the duty cycle will be set at 1.5/5 × 100% or 30% by the feedback loop. This will give roughly a 540ns on-time for QT and a 1.26 µs on-time for QB. This constant frequency operation brings with it a couple of benefits. Inductor and capacitor values can be chosen with a precise operating frequency in mind and the feed- back loop components can be similarly tightly specified. Noise generated by the circuit will always be in a known frequency band with the 550kHz frequency designed to leave the 455kHz IF band free of interference. Subharmonic oscillation and slope compensation, common headaches with constant frequency current mode switchers, are absent in voltage mode designs like the LTC1873. During the time that QT is on, its source (the SW pin) is at VIN. VIN is also the power supply for the LTC1873. How- ever, QT requires VIN + VGS(ON) at its gate to achieve minimum RON. This presents a problem for the LTC1873— it needs to generate a gate drive signal at TG higher than its highest supply voltage. To accomplish this, the TG driver runs from floating supplies, with its negative supply attached to SW and its power supply at BOOST. This allows it to slew up and down with the source of QT. In combination with a simple external charge pump (Figure 2), this allows the LTC1873 to completely enhance the gate of QT without requiring an additional, higher supply voltage. The two channels of the LTC1873 run from a common clock, with the phasing chosen to be 180 ° from side 1 to side 2. This has the effect of doubling the frequency of the switching pulses seen by the input bypass capacitor, significantly lowering the RMS current seen by the capaci- tor and reducing the value required (see the 2-Phase section). Feedback Amplifier Each side of the LTC1873 senses the output voltage at VOUT with an internal feedback op amp (see Block Dia- gram). This is a real op amp with a low impedance output, 85dB open-loop gain and 25MHz gain-bandwidth product. The positive input is connected internally to an 800mV reference, while the negative input is connected to the FB Figure 1. Synchronous Buck Architecture + TG 1/2 LTC1873 BG SW PGND COUT 1873 F01 + CIN QT QB VOUT VIN LEXT Figure 2. Floating TG Driver Supply + TG BOOST SW BG PGND PVCC DCP CIN + COUT 1873 F02 VOUT LEXT VIN QT QB CCP 1 µF LTC1873 APPLICATIO S I FOR ATIO |
Similar Part No. - LTC1873 |
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Similar Description - LTC1873 |
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