11

LTC1878

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of

internal top and bottom switches. Both the DC bias and

their effects will be more pronounced at higher supply

voltages.

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

(DC) as follows:

be obtained from the Typical Performance Charateristics

output current.

losses and inductor core losses generally account for less

than 2% total additional loss.

LOAD CURRENT (mA)

0.1

1

0.00001

0.001

1

10

100

1000

1878 F06

0.0001

0.01

0.1

L = 10

µH

Burst Mode OPERATION

Figure 6. Power Lost vs Load Current

APPLICATIO S I FOR ATIO

external and internal frequencies are the same but exhibit

a phase difference, the current sources turn on for an

amount of time corresponding to the phase difference.

Thus the voltage on the PLL LPF pin is adjusted until the

phase and frequency of the external and internal oscilla-

tors are identical. At this stable operating point the phase

comparator output is high impedance and the filter

current pulses from the phase detector and provide a

stable input to the voltage controlled oscillator. The filter

0.01

µF. When not synchronized to an external clock, the

internal connection to the VCO is disconnected. This

disallows setting the internal oscillator frequency by a DC

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

loss dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence as illustrated in Figure 6.

the DC bias current as given in the electrical character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the