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LTC2424C Datasheet(PDF) 7 Page - Linear Technology

Part # LTC2424C
Description  4-/8-Channel 20-Bit uPower No Latency ADCs
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2424C Datasheet(HTML) 7 Page - Linear Technology

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7
LTC2424/LTC2428
FU CTIO AL BLOCK DIAGRA
TEST CIRCUITS
3.4k
SDO
24248 TC01
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
3.4k
SDO
24248 TC02
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
CLOAD = 20pF
VCC
AUTOCALIBRATION
AND CONTROL
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
CHANNEL
SELECT
ADC
DAC
GND
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
VCC
SDO
SCK
FSSET
ZSSET
CSADC
FO
(INT/EXT)
24248 BD
CSMUX
DIN
CLK
APPLICATIONS INFORMATION
Converter Operation Cycle
The LTC2424/LTC2428 are low power, 4-/8-channel delta-
sigma analog-to-digital converters with easy-to-use
4-wire interfaces. Their operation is simple and made up
of four states. The converter operation begins with the
conversion, followed by a low power sleep state and
concluded with the data output (see Figure 1). Channel
selection may be performed while the device is in the sleep
state or at the conclusion of the data output state. The
interface consists of serial data output (SDO), serial clock
(CLK/SCK), chip select (CSADC/CSMUX) and data input
(DIN). By tying SCK to CLK and CSADC to CSMUX, the
interface requires only four wires.
Initially, the LTC2424 or LTC2428 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by an order of magnitude. The part remains in
the sleep state as long as CSADC is logic HIGH. The
conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Channel selection for the next conversion cycle is per-
formed while the device is in the sleep state or at the end


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