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LTC2428C Datasheet(PDF) 5 Page - Linear Technology |
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LTC2428C Datasheet(HTML) 5 Page - Linear Technology |
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5 / 28 page  5 LTC2424/LTC2428 The q denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) fEOSC External Oscillator Frequency Range 20-Bit Effective Resolution q 2.56 307.2 kHz 12-Bit Effective Resolution q 2.56k 2.048M Hz tHEO External Oscillator High Period q 0.5 390 µs tLEO External Oscillator Low Period q 0.5 390 µs tCONV Conversion Time FO = 0V q 130.66 133.33 136 ms FO = VCC q 156.80 160 163.20 ms External Oscillator (Note 11) q 20480/fEOSC (in kHz) ms fISCK Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz External Oscillator (Notes 10, 11) fEOSC/8 kHz DISCK Internal SCK Duty Cycle (Note 10) 45 55 % fESCK External SCK Frequency Range (Note 9) q 2000 kHz tLESCK External SCK Low Period (Note 9) q 250 ns tHESCK External SCK High Period (Note 9) q 250 ns tDOUT_ISCK Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) q 1.23 1.25 1.28 ms External Oscillator (Notes 10, 11) q 192/fEOSC (in kHz) ms tDOUT_ESCK External SCK 24-Bit Data Output Time (Note 9) q 24/fESCK (in kHz) ms t1 CS ↓ to SDO Low Z q 0 150 ns t2 CS ↑ to SDO High Z q 0 150 ns t3 CS ↓ to SCK ↓ (Note 10) q 0 150 ns t4 CS ↓ to SCK ↑ (Note 9) q 50 ns tKQMAX SCK ↓ to SDO Valid q 200 ns tKQMIN SDO Hold After SCK ↓ (Note 5) q 15 ns t5 SCK Set-Up Before CS ↓ q 50 ns t6 SCK Hold After CS ↓ q 50 ns SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: All voltage values are with respect to GND. Note 3: VCC = 2.7 to 5.5V unless otherwise specified, source input is 0 Ω. CSADC = CSMUX = CS. VREF = FSSET – ZSSET. Note 4: Internal Conversion Clock source with the FO pin tied to GND or to VCC or to external conversion clock source with fEOSC = 153600Hz unless otherwise specified. Note 5: Guaranteed by design, not subject to test. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2% (external oscillator). Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2% (external oscillator). Note 9: The converter is in external SCK mode of operation such that the SCK pin is used as digital input. The frequency of the clock signal driving SCK during the data output is fESCK and is expressed in kHz. Note 10: The converter is in internal SCK mode of operation such that the SCK pin is used as digital output. In this mode of operation the SCK pin has a total equivalent load capacitance CLOAD = 20pF. Note 11: The external oscillator is connected to the FO pin. The external oscillator frequency, fEOSC, is expressed in kHz. Note 12: The converter uses the internal oscillator. FO = 0V or FO = VCC. Note 13: The output noise includes the contribution of the internal calibration operations. Note 14: For reference voltage values VREF > 2.5V the extended input of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤ 0.267V + 0.89 • VCC the input voltage range is – 0.3V to 1.125 • VREF. For 0.267V + 0.89 • VCC < VREF ≤ VCC the input voltage range is – 0.3V to VCC + 0.3V. Note 15: VS is the voltage applied to a channel input. VD is the voltage applied to the MUX output. Note 16: VCC(DC) = 4.1V, VCC(AC) = 2.8VP-P. TI I G CHARACTERISTICS |
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